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  • Avalon_VGA

    Avalon_VGA,-- This design provides an interface to the Alcahest VGA daughter card. -- The design comprises of an 8-bit VGA driver with Avalon bus interfaces. There are a total of -- three Avalon interfaces.

    標簽: Avalon_VGA

    上傳時間: 2015-07-07

    上傳用戶:kikye

  • Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL c

    Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model

    標簽: Algorithm Decoder DVB-RCS Release

    上傳時間: 2015-07-10

    上傳用戶:清風冷雨

  • 關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in

    關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

    標簽: investigates implementing pipelines circuits

    上傳時間: 2015-07-26

    上傳用戶:CHINA526

  • The objective of this projectis to design, model and simulate an autocorrelation generator circuit

    The objective of this projectis to design, model and simulate an autocorrelation generator circuit using 4-bit LFSR. the register and LFSR will used D flip-flop and some gates. By the autocorrelation concept, there should be 2 same length vectors, for calculating the autocorrelation , we have to design the register for storing the original vector and the shifter for make time delay.

    標簽: autocorrelation objective generator projectis

    上傳時間: 2015-08-17

    上傳用戶:ikemada

  • 邏輯分析儀 PC發送到單片機的命令共7個字節: 第一字節是觸發信號

    邏輯分析儀 PC發送到單片機的命令共7個字節: 第一字節是觸發信號,每bit對應一路信號,1為高電平觸發,0為低電平觸發; 第二字節是觸發有效信號,每bit對應一路信號,1為忽略,0為有效; 第三、四字節是采樣時間,對應如下: 2us=0x0402,5us=0x0a02,10us=0x1402,10us=0x2802,50us=0x6402,100us=0xc802,200us=0x3203,500us=0x7d03,1ms=0xfa03,2ms=0x7d04,4ms=0xfa04,8ms=0x7d05,16ms=0xfa05; 第五、六字節是一樣的,為預觸發:8=0%,7=12.5%,6=25%,5=37.5%,4=50%,3=62.5%,2=75%,1=87.5% 第七字節為模式,0=普通模式;1=外部時鐘,上升延;2=外部時鐘,下降延;3=外部觸發,上升延;4=外部觸發,下降延;5=靜態模式;6沒有查到,不知道是什么;7為測試模式的二進制信號;8為測試模式的AA、55;9為測試模式的清零。

    標簽: 字節 邏輯分析儀 發送 單片機

    上傳時間: 2013-12-12

    上傳用戶:luke5347

  • Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols.

    Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register.

    標簽: symbols length Hard-decision Codeword

    上傳時間: 2014-07-08

    上傳用戶:曹云鵬

  • 由delphi實現的bt下載器示例程序

    由delphi實現的bt下載器示例程序,帶全部源碼和BT協議 包中文件說明: BTDemo.dpr, BTDemoF.pas, BTDemoF.dfm -- 一個簡單的bt下載器,支持多個.torrent文件同時下載 btutils.pas -- 核心bt組件 DCP*.pas -- SHA算法源碼(復制自DEC組件包) InetUtils.pas -- 提供Internet下載的函數庫 SimpleSocks.pas -- socket組件(TCP) SortLists.pas -- 排序的List組件 ThreadTimer.pas -- 定時器與線程池 DelayLists.pas -- 一個延時5秒再釋放Object的隊列 FastShareMem.pas, MemPools.pas, ShareGlobals.inc -- 由ThreadTimer內部使用 bit Torrent Specification.htm -- BT協議文檔

    標簽: delphi 下載器 程序

    上傳時間: 2015-09-10

    上傳用戶:lizhen9880

  • /*** *** *** *** *** *** *** *** *** *** *** *** **/ //**此映射表用來映射LED模塊不譯碼時

    /*** *** *** *** *** *** *** *** *** *** *** *** **/ //**此映射表用來映射LED模塊不譯碼時,顯示的字符和必須輸入的數據的關系 //**每段和對應比特位的關系見示意圖 // g // --- --- // b | a |f | | <---顯示0時點亮的段為gfedcb // --- // c | |e | | 那么寫入數據為0x7e // --- --- // d // bit: 7 6 5 4 3 2 1 0 // 段位: g f e d c b a

    標簽: LED 映射 模塊 譯碼

    上傳時間: 2013-11-25

    上傳用戶:

  • the c languge is used for the GPS field.The pogram is the PARITY CHECK ,which is one kind data of th

    the c languge is used for the GPS field.The pogram is the PARITY CHECK ,which is one kind data of the GPS data .and it is used for correcting one bit error

    標簽: the is languge PARITY

    上傳時間: 2013-11-26

    上傳用戶:xiaodu1124

  • sd2003芯片資料及源碼

    sd2003芯片資料及源碼,C51下的,可以直接使用,不是廠方提供的測試程序, 相應子程序: extern void ini_SD2003(void) extern bit mend_scl_SD2003(void) extern bit start_bit_SD2003(void) extern void stop_bit_SD2003(void) extern void ack_SD2003(void) extern void no_ack_SD2003(void) extern void mast_ack_SD2003(void) extern void write_8bit_SD2003(UCHAR ch) extern UCHAR Read_8bit_SD2003(void) extern void write_8bit_SD2003_R(UCHAR ch) extern UCHAR Read_8bit_SD2003_R(void) extern bit Readblock_SD2003(UCHAR ucommand,UCHAR *p) extern bit Writeblock_SD2003(UCHAR ucommand,UCHAR *p)

    標簽: 2003 sd 芯片資料 源碼

    上傳時間: 2015-09-14

    上傳用戶:zl5712176

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