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bits

Microchip公司PIC18F4550芯片的USB firmware代碼

Microchip公司PIC18F4550芯片的USB firmware代碼，我在壓縮包中添加了jpg格式的硬件連接原理圖和MPLAB IDE下的config bits配置圖，希望對大家有用。

標簽： Microchip firmware F4550 4550

上傳時間： 2015-05-10

上傳用戶：英雄
The Viterbi algorithm is the same as the binary case with one main difference: The survivor sequence

The Viterbi algorithm is the same as the binary case with one main difference: The survivor sequences include the uncoded bits, which are decided at each trellis stage when selecting one of two parallel branches with the largest correlation metric. Presently, only 8-PSK modulation is considered. Extensions to higher-order modulations can be implemented following a similar procedure.

標簽： difference The algorithm the

上傳時間： 2015-07-05

上傳用戶：qiaoyue
The program was written with some object-orientation in mind, which means that all functions that op

The program was written with some object-orientation in mind, which means that all functions that operate on a certain structure, has the structure s name as prefix in the function name, for example "bitstream_get" which gets bits from a bitstream structure.

標簽： object-orientation that functions program

上傳時間： 2014-01-15

上傳用戶：epson850
C# BigInteger class. BigInteger.cs is a csharp program. It is the BIgInteger class. It has methods:

C# BigInteger class. BigInteger.cs is a csharp program. It is the BIgInteger class. It has methods: abs() , FermatLittleTest(int confidence) ,gcd(BigInteger bi) , genCoPrime(int bits, Random rand) , genPseudoPrime(int bits, int confidence, Random rand) , genRandombits(int bits, Random rand) , isProbablePrime(int confidence) , isProbablePrime() , Jacobi(BigInteger a, BigInteger b) , LucasSequence(BigInteger P, BigInteger Q, BigInteger k, BigInteger n) ,max(BigInteger bi) , min(BigInteger bi) , modInverse(BigInteger modulus) , RabinMillerTest(int confidence) ,

標簽： BigInteger class BIgInteger program

上傳時間： 2013-12-23

上傳用戶：ynzfm
VHDL實現SPI功能源代碼 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register betw

VHDL實現SPI功能源代碼 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.

標簽： SPI bus register effect

上傳時間： 2013-12-23

上傳用戶：lx9076
The programming port of all the FP PLC’s support OPEN MEWTOCOL-COM. This is very useful when you wan

The programming port of all the FP PLC’s support OPEN MEWTOCOL-COM. This is very useful when you want to monitor PLC values/bits or to set PLC values or bits via your COMPUTER. You can use any language such as Basic, C, Pascal, Assembler or even if other suppliers of PLCs can send ASCII strings, they can talk to our PLCs to exchange data.

標簽： MEWTOCOL-COM programming support useful

上傳時間： 2015-12-08

上傳用戶：youmo81
Author: wei liu Summary: simulation of binary and non-binary bch decoder MATLAB Release: R1

Author: wei liu Summary: simulation of binary and non-binary bch decoder MATLAB Release: R14SP1 Required Products: Communications Toolbox Description: simulation of binary bch decoding algorithm for bch(n, k) with t bits error correction capability.

標簽： simulation non-binary Summary Release

上傳時間： 2014-01-10

上傳用戶：frank1234
this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 compu

this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.

標簽： implementation include quartus source

上傳時間： 2013-12-25

上傳用戶：壞壞的華仔
Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO

Synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.

標簽： FIFO implementation Synthesizable synthesizable

上傳時間： 2016-02-12

上傳用戶：源弋弋
. Info directory .delphiinternet Delphi sample applications (all Delphi versions) .cppinternet C++

.\ Info directory .\delphi\internet Delphi sample applications (all Delphi versions) .\cpp\internet C++Builder sample applications .\cpp\internet\bcb1 C++Builder version 1 projects .\cpp\internet\bcb3 C++Builder version 3 projects .\cpp\internet\bcb4 C++Builder version 4 projects .\cpp\internet\bcb5 C++Builder version 5 projects .\cpp\internet\bcb6 C++Builder version 6 projects .\delphi\vc Delphi 1.x files (winsock.pas 16 bits and *.dcr) .\delphi\vc32 Delphi (1/2/3/4/5/6/7) and C++Builder (1/3/4/5/6) components .\Delphi1 Automated build for Delphi 1. Not for beginners. .\Delphi2 Automated build for Delphi 2. Not for beginners. .\Delphi3 Automated build for Delphi 3. Not for beginners. .\bcb1 Automated build for Bcb 1. Not for beginners.

標簽： Delphi delphiinternet applications cppinternet

上傳時間： 2014-01-12

上傳用戶：star_in_rain

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