Digital cameras have become increasingly popular over the last few years. Digital imagingtechnology has grown to new markets including cellular phones and PDA deviCEs. With thediverse marketplace, a variety of imaging technology must be available. Imaging technologyhas expanded to include both charge-coupled device (CCD) and CMOS image sensors.
標(biāo)簽： CoolRunner-II XAPP CPLD 390
上傳時(shí)間： 2013-10-16
上傳用戶：18710733152
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer deviCEs. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
標(biāo)簽： Spartan XAPP 1065 FPGA
上傳時(shí)間： 2013-11-01
上傳用戶：hjkhjk
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These deviCEs enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上傳時(shí)間： 2013-12-07
上傳用戶：bruce
SRAM-based FPGAs are non-volatile deviCEs. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
標(biāo)簽： FPGA PLD 數(shù)據(jù)加密
上傳時(shí)間： 2013-10-20
上傳用戶：磊子226
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware deviCEs. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： CPLD
上傳時(shí)間： 2014-12-05
上傳用戶：qazxsw
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT deviCEs. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標(biāo)簽： Transceiver Virtex Wizar GTP
上傳時(shí)間： 2013-10-20
上傳用戶：dave520l
ref-sdr-sdram-vhdl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) deviCEs. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上傳時(shí)間： 2013-10-23
上傳用戶：半熟1994
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express deviCEs located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶：s363994250
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx deviCEs lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
標(biāo)簽： 賽靈思 電機(jī)控制 開(kāi)發(fā)套件 英文
上傳時(shí)間： 2013-10-28
上傳用戶：wujijunshi
西門(mén)子建筑電器-電氣安裝技術(shù)部發(fā)行的各類產(chǎn)品樣本：小型斷路器、剩余電流保護(hù)斷路器和模數(shù)化產(chǎn)品(中/ 英文)Miniature Circuit-Breakers, Residual Current Operated Circuit-Breakers and Modular deviCEs (Chinese/English)低壓熔斷器系統(tǒng)(中/ 英文)Fuse System (Chinese/English)雷擊，過(guò)電壓－不再是問(wèn)題(中文)Thunderstorms - no problem (Chinese)西門(mén)子建筑電器目錄(中文)Electrical Installation Technology Catalog (Chinese)終端配電保護(hù)產(chǎn)品(中文)5 IN 1 (Chinese)SIKUS 和 STAB UNIVERSAL 目錄(中文)SIKUS and STAB UNIVERSAL Catalogue (Chinese)SIKUS HC 目錄(中文)SIKUS HC Catalogue (Chinese)SentronTM 母線槽 (中文)SentronTM Busway System (Chinese)SentronTM 母線槽系統(tǒng)快速選型 (準(zhǔn)備中) (中文)SentronTM Busway System quick selection (in preparing) (Chinese)建筑低壓配電一體化解決方案－住宅小區(qū)應(yīng)用(中文)Building LV PD Solution (Chinese)西門(mén)子 DELTA vista“遠(yuǎn)景”系列開(kāi)關(guān)和插座價(jià)目表(中文)Delta vista Switch and Socket Pricelist (Chinese)instabus EIB 面向未來(lái)的樓宇智能控制系統(tǒng)(中文)instabus EIB (Chinese)instabus EIB 面向未來(lái)的樓宇智能控制系統(tǒng)技術(shù)手冊(cè) (準(zhǔn)備中) (中文)instabus EIB technical handbook (in preparing) (Chinese)西門(mén)子電氣安裝技術(shù)業(yè)績(jī)卓越(中/ 英文)ET Reference Manual (Chinese/English)
上傳時(shí)間： 2013-11-23
上傳用戶：瓦力瓦力hong
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
