MAXQUSBJTAGOW評估板軟件:關鍵特性 easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
MAXQUSBJTAGOW評估板軟件:關鍵特性 easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
本文利用Verilog HDL 語言自頂向下的設計方法設計多功能數字鐘，突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優點，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應用于實際的數字鐘顯示中。
關鍵詞：Verilog HDL；硬件描述語言；FPGA
Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip.
Keywords: Verilog HDL；hardware description language；FPGA
UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_vhdl
This zip file contains the following folders:
\vhdl_source -- Source VHDL files:
uart.vhd - top level file
txmit.vhd - transmit portion of uart
rcvr.vhd - - receive portion of uart
\vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they
do not instantiate the DUT. This can easily be done in a top-level VHDL
file or a schematic. This folder contains the following files:
txmit_tb.vhd -- Test bench for txmit.vhd.
rcvr_tf.vhd -- Test bench for rcvr.vhd.
手機文件瀏覽器 Here are the sources to SMan v1.2c 1.2 is a major jump from v1.1. You will see this from the way the code has been restructured into multiple files. It also supports flip closed. However, to my chagrin, I made the mistake of assuming there will only be one flip closed view. :( That s changed in v1.3 :) 1.3 supports multiple flip closed views that can be easily added into SMan.
LIBSVM is an integrated software for support vector classification. LIBSVM provides a simple interface where users can easily link it with their own programs.
項目描述:
Trickster Streaming Server is a pure Perl MP3 streaming server with a simple Web interface that allows you to manipulate and browse the queue. The queue management API is done in a fairly simple UNIX manner, and can be easily extended.
Trickster Streaming Server是一個具有簡單 Web接口的純 Perl MP3流服務器，它讓你操作并瀏覽隊列。這個隊列管理 API 用一種相當簡單的UNIX方式來做，并能被容易的擴展。
自制51編程器
I have build my own programmer. This device can program the AT89C51 and works with it. So it can easily be adapted to programming other devices by itself.
The Atmel Flash devices are ideal for developing, since they can be reprogrammed easy, often and fast. You need only 1 or 2 devices in low cost plastic case for developing. In contrast you need 10 or more high cost windowed devices if you must develop with EPROM devices (e.g. Phillips 87C751).
