Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
上傳時間： 2014-01-11
上傳用戶：a471778
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標簽： CoolRunner-II XAPP CPLD 380
上傳時間： 2013-10-26
上傳用戶：kiklkook
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
上傳時間： 2013-12-14
上傳用戶：逗逗666
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達到了預(yù)期的設(shè)計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計
上傳時間： 2013-10-28
上傳用戶：jyycc
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標簽： pci PCB 設(shè)計規(guī)范
上傳時間： 2014-01-24
上傳用戶：s363994250
為了提高直接轉(zhuǎn)矩控制（DTC）系統(tǒng)定子磁鏈估計精度，降低電流、電壓測量的隨機誤差，提出了一種基于擴展卡爾曼濾波（EKF）實現(xiàn)異步電機轉(zhuǎn)子位置和速度估計的方法。擴展卡爾曼濾波器是建立在基于旋轉(zhuǎn)坐標系下由定子電流、電壓、轉(zhuǎn)子轉(zhuǎn)速和其它電機參量所構(gòu)成的電機模型上，將定子電流、定子磁鏈、轉(zhuǎn)速和轉(zhuǎn)子角位置作為狀態(tài)變量，定子電壓為輸入變量，定子電流為輸出變量，通過對磁鏈和轉(zhuǎn)速的閉環(huán)控制提高定子磁鏈的估計精度，實現(xiàn)了異步電機的無速度傳感器直接轉(zhuǎn)矩控制策略，仿真結(jié)果驗證了該方法的可行性,提高了直接轉(zhuǎn)矩的控制性能。 Abstract: In order to improve the Direct Torque Control（DTC） system of stator flux estimation accuracy and reduce the current， voltage measurement of random error， a novel method to estimate the speed and rotor position of asynchronous motor based on extended Kalman filter was introduced. EKF was based on d-p axis motor and other motor parameters （state vector: stator current， stator flux linkage， rotor angular speed and position； input: stator voltage； output: staror current). EKF was designed for stator flux and rotor speed estimation in close-loop control. It can improve the estimated accuracy of stator flux. It is possible to estimate the speed and rotor position and implement asynchronous motor drives without position and speed sensors. The simulation results show it is efficient and improves the control performance.
標簽： EKF 異步電機 直接轉(zhuǎn)矩 控制系統(tǒng)
上傳時間： 2015-01-02
上傳用戶：qingdou
Accurate measurement of the third order intercept pointfor low distortion IC products such as the LT5514 requirescertain precautions to be observed in the test setup andtesting procedure. The LT5514 linearity performance ishigh enough to push the test equipment and test set-up totheir limits. A method for accurate measurement of thirdorder intermodulation products, IM3, with standard testequipment is outlined below.It is also important to correctly interpret the LT5514specification with respect to ROUT, and the impact ofdemo-board transmission-line termination loss whenevaluating the linearity performance, as explained in theLT5514 Datasheet and in Note 1 of this document.
標簽： 5514 LT 三階互調(diào) 精確測量
上傳時間： 2013-11-14
上傳用戶：l254587896
基于通用集成運算放大器，利用MASON公式設(shè)計了一個多功能二階通用濾波器，能同時或分別實現(xiàn)低通、高通和帶通濾波，也能設(shè)計成一個正交振蕩器。電路的極點頻率和品質(zhì)因數(shù)能夠獨立、精確地調(diào)節(jié)。電路使用4個集成運放、2個電容和11個電阻，所有集成運放的反相端虛地。利用計算機仿真電路的通用濾波功能、極點頻率和品質(zhì)因數(shù)的獨立控制和正交正弦振蕩，從而證明該濾波器正確有效。 Abstract: A new multifunctional second-order filter based on OPs was presented by MASON formula. Functions， such as high-pass， band-pass， low-pass filtering， can be realized respectively and simultaneously， and can become a quadrature oscillator by modifying resistance ratio. Its pole angular frequency and quality factor can be tuned accurately and independently. The circuit presented contains four OPs， two capacitors， and eleven resistances， and inverting input of all OPs is virtual ground. Its general filtering， the independent control of pole frequency and quality factor and quadrature sinusoidal oscillation were simulated by computer， and the result shows that the presented circuit is valid and effective.
標簽： MASON 多功能 二階 濾波器設(shè)計
上傳時間： 2013-10-09
上傳用戶：13788529953
A windows BMP file is a common image format that Java does not handle. While BMP images are used only on windows machines, they are reasonably common. Reading these shows how to read complex structures in Java and how to alter they byte order from the big endian order used by Java to the little endian order used by the windows and the intel processor.
上傳時間： 2013-12-27
上傳用戶：gaojiao1999
ZipForge is a fast ZIP compression library. With this toolkit you can easily add archive functionality to your projects. ZipForge includes our new unique techonology, a transaction system. This innovative solution gives you a fast and easy way of updating archive files providing data integrity like a reliable database system. ZipForge Personal is free for personal use. Any company that uses ZipForge in its projects must order ZipForge Pro.
標簽： compression functionali ZipForge archive
上傳時間： 2014-11-28
上傳用戶：520
蟲蟲下載站版權(quán)所有 京ICP備2021023401號-1
