The P82B96 offers many different ways in which it can be used as abus interface. In its simplest application it can be used as aninterface between bus systems operating from different supplyvoltages. Opto isolation between two bus systems is possible, andalso the availability of the Tx and Rx signals permits interfacing ofthe P82B96 with other bus systems which separate the forwardoutput path, from the backward input signal path.
上傳時間： 2013-10-11
上傳用戶：洛木卓
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上傳時間： 2013-10-23
上傳用戶：copu
有兩種方式可以讓設備和應用程序之間聯系：1. 通過為設備創建的一個符號鏈；2. 通過輸出到一個接口WDM驅動程序建議使用輸出到一個接口而不推薦使用創建符號鏈的方法。這個接口保證PDO的安全，也保證安全地創建一個惟一的、獨立于語言的訪問設備的方法。一個應用程序使用Win32APIs來調用設備。在某個Win32 APIs和設備對象的分發函數之間存在一個映射關系。獲得對設備對象訪問的第一步就是打開一個設備對象的句柄。 用符號鏈打開一個設備的句柄為了打開一個設備，應用程序需要使用CreateFile。如果該設備有一個符號鏈出口，應用程序可以用下面這個例子的形式打開句柄：hDevice = CreateFile("\\\\.\\OMNIPORT3", GENERIC_READ | GENERIC_WRITE,FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL ,NULL);文件路徑名的前綴“\\.\”告訴系統本調用希望打開一個設備。這個設備必須有一個符號鏈，以便應用程序能夠打開它。有關細節查看有關Kdevice和CreateLink的內容。在上述調用中第一個參數中前綴后的部分就是這個符號鏈的名字。注意：CreatFile中的第一個參數不是Windows 98/2000中驅動程序(.sys文件)的路徑。是到設備對象的符號鏈。如果使用DriverWizard產生驅動程序，它通常使用類KunitizedName來構成設備的符號鏈。這意味著符號鏈名有一個附加的數字，通常是0。例如：如果鏈接名稱的主干是L“TestDevice”那么在CreateFile中的串就該是“\\\\.\\TestDevice0”。如果應用程序需要被覆蓋的I/O，第六個參數(Flags)必須或上FILE_FLAG_OVERLAPPED。 使用一個輸出接口打開句柄用這種方式打開一個句柄會稍微麻煩一些。DriverWorks庫提供兩個助手類來使獲得對該接口的訪問容易一些，這兩個類是CDeviceInterface, 和 CdeviceInterfaceClass。CdeviceInterfaceClass類封裝了一個設備信息集，該信息集包含了特殊類中的所有設備接口信息。應用程序能有用CdeviceInterfaceClass類的一個實例來獲得一個或更多的CdeviceInterface類的實例。CdeviceInterface類是一個單一設備接口的抽象。它的成員函數DevicePath()返回一個路徑名的指針，該指針可以在CreateFile中使用來打開設備。下面用一個小例子來顯示這些類最基本的使用方法：extern GUID TestGuid;HANDLE OpenByInterface( GUID* pClassGuid, DWORD instance, PDWORD pError){ CDeviceInterfaceClass DevClass(pClassGuid, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; CDeviceInterface DevInterface(&DevClass, instance, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; cout << "The device path is " << DevInterface.DevicePath() << endl; HANDLE hDev; hDev = CreateFile( DevInterface.DevicePath(), GENERIC_READ | GENERIC_WRITE, FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL ); if (hDev == INVALID_HANDLE_VALUE) *pError = GetLastError(); return hDev;} 在設備中執行I/O操作一旦應用程序獲得一個有效的設備句柄，它就能使用Win32 APIs來產生到設備對象的IRPs。下面的表顯示了這種對應關系。Win32 API DRIVER_FUNCTION_xxxIRP_MJ_xxx KDevice subclass member function CreateFile CREATE Create ReadFile READ Read WriteFile WRITE Write DeviceIoControl DEVICE_CONTROL DeviceControl CloseHandle CLOSECLEANUP CloseCleanUp 需要解釋一下設備類成員的Close和CleanUp：CreateFile使內核為設備創建一個新的文件對象。這使得多個句柄可以映射同一個文件對象。當這個文件對象的最后一個用戶級句柄被撤銷后，I/O管理器調用CleanUp。當沒有任何用戶級和核心級的對文件對象的訪問的時候，I/O管理器調用Close。如果被打開的設備不支持指定的功能，則調用相應的Win32將引起錯誤（無效功能）。以前為Windows95編寫的VxD的應用程序代碼中可能會在打開設備的時候使用FILE_FLAG_DELETE_ON_CLOSE屬性。在Windows NT/2000中，建議不要使用這個屬性，因為它將導致沒有特權的用戶企圖打開這個設備，這是不可能成功的。I/O管理器將ReadFile和WriteFile的buff參數轉換成IRP域的方法依賴于設備對象的屬性。當設備設置DO_DIRECT_IO標志，I/O管理器將buff鎖住在存儲器中，并且創建了一個存儲在IRP中的MDL域。一個設備可以通過調用Kirp::Mdl來存取MDL。當設備設置DO_BUFFERED_IO標志，設備對象分別通過KIrp::BufferedReadDest或 KIrp::BufferedWriteSource為讀或寫操作獲得buff地址。當設備不設置DO_BUFFERED_IO標志也不設置DO_DIRECT_IO，內核設置IRP 的UserBuffer域來對應ReadFile或WriteFile中的buff參數。然而，存儲區并沒有被鎖住而且地址只對調用進程有效。驅動程序可以使用KIrp::UserBuffer來存取IRP域。對于DeviceIoControl調用，buffer參數的轉換依賴于特殊的I/O控制代碼，它不在設備對象的特性中。宏CTL_CODE（在winioctl.h中定義）用來構造控制代碼。這個宏的其中一個參數指明緩沖方法是METHOD_BUFFERED, METHOD_IN_DIRECT, METHOD_OUT_DIRECT, 或METHOD_NEITHER。下面的表顯示了這些方法和與之對應的能獲得輸入緩沖與輸出緩沖的KIrp中的成員函數：Method Input Buffer Parameter Output Buffer Parameter METHOD_BUFFERED KIrp::IoctlBuffer KIrp::IoctlBuffer METHOD_IN_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_OUT_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_NEITHER KIrp::IoctlType3InputBuffer KIrp::UserBuffer 如果控制代碼指明METHOD_BUFFERED，系統分配一個單一的緩沖來作為輸入與輸出。驅動程序必須在向輸出緩沖放數據之前拷貝輸入數據。驅動程序通過調用KIrp::IoctlBuffer獲得緩沖地址。在完成時，I/O管理器從系統緩沖拷貝數據到提供給Ring 3級調用者使用的緩沖中。驅動程序必須在結束前存儲拷貝到IRP的Information成員中的數據個數。如果控制代碼不指明METHOD_IN_DIRECT或METHOD_OUT_DIRECT，則DeviceIoControl的參數呈現不同的含義。參數InputBuffer被拷貝到一個系統緩沖，這個緩沖驅動程序可以通過調用KIrp::IoctlBuffer。參數OutputBuffer被映射到KMemory對象，驅動程序對這個對象的訪問通過調用KIrp::Mdl來實現。對于METHOD_OUT_DIRECT，調用者必須有對緩沖的寫訪問權限。注意，對METHOD_NEITHER，內核只提供虛擬地址；它不會做映射來配置緩沖。虛擬地址只對調用進程有效。這里是一個用METHOD_BUFFERED的例子：首先，使用宏CTL_CODE來定義一個IOCTL代碼：#define IOCTL_MYDEV_GET_FIRMWARE_REV \CTL_CODE (FILE_DEVICE_UNKNOWN,0,METHOD_BUFFERED,FILE_ANY_ACCESS)現在使用一個DeviceIoControl調用：BOOLEAN b;CHAR FirmwareRev[60];ULONG FirmwareRevSize;b = DeviceIoControl(hDevice, IOCTL_MYDEV_GET_VERSION_STRING, NULL, // no input 注意，這里放的是包含有執行操作命令的字符串指針 0, FirmwareRev, //這里是output串指針，存放從驅動程序中返回的字符串。sizeof(FirmwareRev),& FirmwareRevSize, NULL // not overlapped I/O );如果輸出緩沖足夠大，設備拷貝串到里面并將拷貝的資結束設置到FirmwareRevSize中。在驅動程序中，代碼看起來如下所示：const char* FIRMWARE_REV = "FW 16.33 v5";NTSTATUS MyDevice::DeviceControl( KIrp I ){ ULONG fwLength=0; switch ( I.IoctlCode() ) { case IOCTL_MYDEV_GET_FIRMWARE_REV: fwLength = strlen(FIRMWARE_REV)+1; if (I.IoctlOutputBufferSize() >= fwLength) { strcpy((PCHAR)I.IoctlBuffer(),FIRMWARE_REV); I.Information() = fwLength; return I.Complete(STATUS_SUCCESS); } else { } case . . . } }
上傳時間： 2013-10-17
上傳用戶：gai928943
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
上傳時間： 2013-10-22
上傳用戶：taiyang250072
為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上傳時間： 2014-01-13
上傳用戶：qoovoop
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上傳時間： 2013-10-24
上傳用戶：s藍莓汁
We offer a broad line of high performance low dropout (LDO) linear regulators with fasttransient response, excellent line and load regulation, and very wide input voltage rangefrom 0.9V to 100V. Output currents range from 20mA to 10A, with positive, negative andmultiple output versions available. Many devices offer output voltage operation <0.8V andsome feature operation as low as 0V, even with a single supply. Most are stable with ceramicoutput capacitors. LDO regulators can be applied in virtually any application.
上傳時間： 2013-11-15
上傳用戶：努力努力再努力
Multioutput monolithic regulators are easy to use and fi tinto spaces where multichip solutions cannot. Nevertheless,the popularity of multioutput regulators is temperedby a lack of options for input voltages above 30V andsupport of high output currents. The LT3692A fi lls thisgap with a dual monolithic regulator that operates frominputs up to 36V. It also includes a number of channeloptimization features that allow the LT3692A’s per-channelperformance to rival that of multichip solutions.
上傳時間： 2014-01-03
上傳用戶：Huge_Brother
超聲波傳感器適用于對大幅的平面進行靜止測距。普通的超聲波傳感器測距范圍大概是 2cm~450cm，分辨率3mm（淘寶賣家說的，筆者測試環境沒那么好，個人實測比較穩定的 距離10cm~2m 左右，超過此距離就經常有偶然不準確的情況發生了，當然不排除筆者技術 問題。） 測試對象是淘寶上面最便宜的SRF-04 超聲波傳感器，有四個腳：5v 電源腳（Vcc），觸發控制端（Trig），接收端（Echo），地端（GND） 附:SRF 系列超聲波傳感器參數比較 模塊工作原理： 采用IO 觸發測距，給至少10us 的高電平信號； 模塊自動發送8個40KHz 的方波，自動檢測是否有信號返回； 有信號返回，通過IO 輸出一高電平，高電平持續的時間就是超聲波從發射到返回的時間．測試距離=(高電平時間*聲速(340m/s))/2; 電路連接方法 Arduino 程序例子： constintTrigPin = 2; constintEchoPin = 3; floatcm; voidsetup() { Serial.begin(9600); pinMode(TrigPin, OUTPUT); pinMode(EchoPin, INPUT); } voidloop() { digitalWrite(TrigPin, LOW); //低高低電平發一個短時間脈沖去TrigPin delayMicroseconds(2); digitalWrite(TrigPin, HIGH); delayMicroseconds(10); digitalWrite(TrigPin, LOW); cm = pulseIn(EchoPin, HIGH) / 58.0; //將回波時間換算成cm cm = (int(cm * 100.0)) / 100.0; //保留兩位小數 Serial.print(cm); Serial.print("cm"); Serial.println(); delay(1000); }
上傳時間： 2013-10-18
上傳用戶：星仔
為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上傳時間： 2013-10-28
上傳用戶：jyycc
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