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modelSim-Altera

ALtera FPGA Cyclone III開發電路圖

ALtera FPGA Cyclone III開發電路圖，對初學者設計此類FPGA有重要參考價值

標簽： Cyclone ALtera FPGA III

上傳時間： 2014-01-13

上傳用戶：稀世之寶039
Modelsim DDR2 SDRAM files

Modelsim DDR2 SDRAM files

標簽： Modelsim SDRAM files DDR2

上傳時間： 2013-12-24

上傳用戶：chenjjer
leon ep2s60 ddr use altera statix2 and add ddr sdram

leon ep2s60 ddr use altera statix2 and add ddr sdram

標簽： ddr statix2 altera sdram

上傳時間： 2017-03-19

上傳用戶：yan2267246
it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x

it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.

標簽： synthesize simulator modelsim interin

上傳時間： 2017-03-22

上傳用戶：洛木卓
it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xin

it is a verilog code written for digital watch in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]

標簽： synthesize simulator modelsim digital

上傳時間： 2014-01-10

上傳用戶：kernaling
it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.

標簽： synthesize simulator modelsim verilog

上傳時間： 2014-06-26

上傳用戶：zhuyibin
采用Altera公司的CycloneII芯片EP2C8的一些程序代碼。

采用Altera公司的CycloneII芯片EP2C8的一些程序代碼。

標簽： CycloneII Altera EP2C8 芯片

上傳時間： 2017-03-23

上傳用戶：xwd2010
Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own fe

Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own female names: ULA and ALA whose are scrolling on the 4-columns crystal LED. When you press the switch it will turn from ULA into ALA and continue scrolling.

標簽： successfully implemented presents Quartus

上傳時間： 2013-12-09

上傳用戶：zjf3110
how to infer ram for fpga altera xilinx

how to infer ram for fpga altera xilinx

標簽： altera xilinx infer fpga

上傳時間： 2013-12-25

上傳用戶：dongbaobao
How to infer a finite state machine for fpga altera xilinx

How to infer a finite state machine for fpga altera xilinx

標簽： machine finite altera xilinx

上傳時間： 2014-01-10

上傳用戶：鳳臨西北

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