Nios 的用戶定義接口邏輯實例 有許多人問我使用 Nios 的用戶定義接口邏輯怎么用，想了幾天決定設計一個實例來說明。該例為一個使用 user to interface logic 設計的 PWM 實例，其中包括三個文件： plus32.v 是一個為 32bit nios 設計的 pwm 實例。 plus16.v 是一個為 16bit nios 設計的 pwm 實例。 test.s 是一個使用中斷調用 pwm 的匯編語言測試程序。以上模塊和程序均調試通過，并可穩(wěn)定工作。這里讓大家參考是使大家通過該例來真正理解 user to interface logic 設計方法，和nios 中通過匯編調用中斷的方法，所以超值喔。另外熱烈歡迎大家的指導。 注：在設計 Nios 時，將你調用的 user to interface logic 插件重命名為 plus_0，這樣我的 test.s 可不作任何改動，你就可用示波器通過 nios 的 plus 管腳觀察到一個要求的輸出。
上傳時間： 2013-11-15
上傳用戶：cc1915
匯編器在微處理器的驗證和應用中舉足輕重，如何設計通用的匯編器一直是研究的熱點之一。本文提出了一種開放式的匯編器系統(tǒng)設計思想，在匯編語言與機器語言間插入中間代碼CMDL（code mapping description language）語言，打破匯編語言與機器語言的直接映射關系，由此建立起一套描述匯編語言與機器語言的開放式映射體系。基于此開放式映射體系開發(fā)了一套匯編器系統(tǒng)，具有較高層次上的通用性和可移植性。【關鍵詞】指令集，CMDL，匯編器，開放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability
上傳時間： 2013-10-10
上傳用戶：meiguiweishi
The main oscillator allows either a crystal or single-ended input clock signal. Cost-sensitiveapplications typically use an external crystal with the on-chip oscillator circuit since it is the mostcost-effective solution. It is also possible to use the internal oscillator to clock the device after theboot process has completed.
標簽： Stellaris Clocking Options for
上傳時間： 2013-10-14
上傳用戶：pol123
基于PIC單片機的脈沖電源:設計了一種金屬凝固過程用脈沖電源。該電源采用PIC16F877作為主控芯片，實現(xiàn)對窄脈沖電流幅值的檢測，以及時電流脈沖幅值根據(jù)模糊PID算法進行閑環(huán)控制。使用結果表明：該電源的輸出脈沖波形良好，電流幅值穩(wěn)定，滿足合金材料凝固過程的工藝要求且運行穩(wěn)定可靠。關鍵詞：脈沖電源；PIC16F877單片機；模糊PID；閑環(huán)控制 Abstract：A kind of pulse power supply was designed which uses in the metal solidification process ．．I11is power supply used PIC16F877 to take the master control chip reali on to the narrow pulse electric current peak-to-peak value examination，carried on the closed-loop control to the electric current pulse peak-to-peak value basis fuzzy PID algorithm．The use result indicated ，this power supply output se profile is good，and the electric current peak-to-p~k value is stable，It satisfies the alloy material solidification process the technological requirement and movement stable reliable，Key words：p se po wer supply；PIC16F877single-chip microcontroller；f r PID；closed-loop control
上傳時間： 2013-10-27
上傳用戶：xcy122677
計算機部件要具有通用性，適應不同系統(tǒng)與不同用戶的需求，設計必須模塊化。計算機部件產(chǎn)品(模塊)供應出現(xiàn)多元化。模塊之間的聯(lián)接關系要標準化，使模塊具有通用性。模塊設計必須基于一種大多數(shù)廠商認可的模塊聯(lián)接關系，即一種總線標準。總線的標準總線是一類信號線的集合是模塊間傳輸信息的公共通道，通過它，計算機各部件間可進行各種數(shù)據(jù)和命令的傳送。為使不同供應商的產(chǎn)品間能夠互換，給用戶更多的選擇，總線的技術規(guī)范要標準化。總線的標準制定要經(jīng)周密考慮，要有嚴格的規(guī)定。總線標準（技術規(guī)范）包括以下幾部分：機械結構規(guī)范：模塊尺寸、總線插頭、總線接插件以及按裝尺寸均有統(tǒng)一規(guī)定。功能規(guī)范：總線每條信號線（引腳的名稱）、功能以及工作過程要有統(tǒng)一規(guī)定。電氣規(guī)范：總線每條信號線的有效電平、動態(tài)轉換時間、負載能力等。總線的發(fā)展情況S-100總線：產(chǎn)生于1975年，第一個標準化總線，為微計算機技術發(fā)展起到了推動作用。IBM-PC個人計算機采用總線結構（Industry Standard Architecture, ISA)并成為工業(yè)化的標準。先后出現(xiàn)8位ISA總線、16位ISA總線以及后來兼容廠商推出的EISA（Extended ISA)32位ISA總線。為了適應微處理器性能的提高及I/O模塊更高吞吐率的要求，出現(xiàn)了VL-Bus(VESA Local Bus)和PCI(Peripheral Component Interconnect,PCI）總線。適合小型化要求的PCMCIA(Personal Computer Memory Card International Association)總線，用于筆記本計算機的功能擴展。總線的指標計算機主機性能迅速提高,各功能模塊性能也要相應提高,這對總線性能提出更高的要求。總線主要技術指標有幾方面：總線寬度：一次操作可以傳輸?shù)臄?shù)據(jù)位數(shù)，如S100為8位，ISA為16位，EISA為32位，PCI-2可達64位。總線寬度不會超過微處理器外部數(shù)據(jù)總線的寬度。總數(shù)工作頻率：總線信號中有一個CLK時鐘，CLK越高每秒鐘傳輸?shù)臄?shù)據(jù)量越大。ISA、EISA為8MHz，PCI為33.3MHz, PCI-2可達達66.6MHz。單個數(shù)據(jù)傳輸周期：不同的傳輸方式，每個數(shù)據(jù)傳輸所用CLK周期數(shù)不同。ISA要2個，PCI用1個CLK周期。這決定總線最高數(shù)據(jù)傳輸率。5. 總線的分類與層次系統(tǒng)總線：是微處理器芯片對外引線信號的延伸或映射，是微處理器與片外存儲器及I/0接口傳輸信息的通路。系統(tǒng)總線信號按功能可分為三類：地址總線（Where）：指出數(shù)據(jù)的來源與去向。地址總線的位數(shù)決定了存儲空間的大小。系統(tǒng)總線：數(shù)據(jù)總線（What）提供模塊間傳輸數(shù)據(jù)的路徑，數(shù)據(jù)總線的位數(shù)決定微處理器結構的復雜度及總體性能。控制總線（When）：提供系統(tǒng)操作所必需的控制信號，對操作過程進行控制與定時。擴充總線：亦稱設備總線，用于系統(tǒng)I/O擴充。與系統(tǒng)總線工作頻率不同，經(jīng)接口電路對系統(tǒng)總統(tǒng)信號緩沖、變換、隔離，進行不同層次的操作（ISA、EISA、MCA)局部總線：擴充總線不能滿足高性能設備（圖形、視頻、網(wǎng)絡）接口的要求，在系統(tǒng)總線與擴充總線之間插入一層總線。由于它經(jīng)橋接器與系統(tǒng)總線直接相連，因此稱之為局部總線（PCI）。
上傳時間： 2013-11-09
上傳用戶：nshark
自制單片機MSP-FET430仿真器 前言：本想到市場買個自制的MSP-FET430仿真工具，但看其做工可不敢恭維。于是打開當時千元購買的FET（1個不夠用啊），又參網(wǎng)上提供的自制FET的資料，依南士接插件的外殼尺寸繪制了自認為布板較合理的PCB使用。上圖為電路參考原型，注意圖中FET 的連接形式（25 針屏蔽電纜轉接線，長度小于20 厘米的扁平線），這樣的連接更利于下載調試的可靠性。.....
上傳時間： 2013-11-20
上傳用戶：xdqm
針對使用硬件描述語言進行設計存在的問題，提出一種基于FPGA并采用DSP Builder作為設計工具的數(shù)字信號處理器設計方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設計流程，設計了一個12階FIR 低通數(shù)字濾波器，通過Quartus 時序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測試對設計進行了驗證。結果表明，所設計的FIR 濾波器功能正確，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
標簽： Builder FPGA DSP 數(shù)字信號處理器
上傳時間： 2013-11-17
上傳用戶：lo25643
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標簽： FPGA 安全系統(tǒng)
上傳時間： 2013-11-05
上傳用戶：維子哥哥
This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.
上傳時間： 2013-11-05
上傳用戶：透明的心情
