The LTC®3207/LTC3207-1 is a 600mA LED/Camera driverwhich illuminates 12 Universal LEDs (ULEDs) and onecamera fl ash LED. The ULEDs are considered universalbecause they may be individually turned on or off, setin general purpose output (GPO) mode, set to blink at aselected on-time and period, or gradate on and off at aselected gradation rate. This device also has an externalenable (ENU) pin that may be used to blink, gradate, orturn on/off the LEDs without using the I2C bus. This may beuseful if the microprocessor is in sleep or standby mode. Ifused properly, these features may save valuable memoryspace, programming time, and reduce the I2C traffi c.
上傳時間： 2014-01-04
上傳用戶：LANCE
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2014-11-26
上傳用戶：erkuizhang
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
第二部分：DRAM 內存模塊的設計技術..............................................................143第一章 SDR 和DDR 內存的比較..........................................................................143第二章 內存模塊的疊層設計.............................................................................145第三章 內存模塊的時序要求.............................................................................1493.1 無緩沖（Unbuffered）內存模塊的時序分析.......................................1493.2 帶寄存器（Registered）的內存模塊時序分析...................................154第四章 內存模塊信號設計.................................................................................1594.1 時鐘信號的設計.......................................................................................1594.2 CS 及CKE 信號的設計..............................................................................1624.3 地址和控制線的設計...............................................................................1634.4 數據信號線的設計...................................................................................1664.5 電源，參考電壓Vref 及去耦電容.........................................................169第五章 內存模塊的功耗計算.............................................................................172第六章 實際設計案例分析.................................................................................178 目前比較流行的內存模塊主要是這三種：SDR，DDR，RAMBUS。其中，RAMBUS內存采用阻抗受控制的串行連接技術,在這里我們將不做進一步探討，本文所總結的內存設計技術就是針對SDRAM 而言(包括SDR 和DDR)。現在我們來簡單地比較一下SDR 和DDR，它們都被稱為同步動態內存，其核心技術是一樣的。只是DDR 在某些功能上進行了改進，所以DDR 有時也被稱為SDRAM II。DDR 的全稱是Double Data rate，也就是雙倍的數據傳輸率，但是其時鐘頻率沒有增加，只是在時鐘的上升和下降沿都可以用來進行數據的讀寫操作。對于SDR 來說,市面上常見的模塊主要有PC100/PC133/PC166,而相應的DDR內存則為DDR200(PC1600)/DDR266(PC2100)/DDR333(PC2700)。
上傳時間： 2013-10-18
上傳用戶：宋桃子
ADAM-5510KW中FPID/PID功能塊之實現及應用一、 ADAM-5510KW實現PID控制的方法1、ADAM-5510KW可以使用Multiprog軟件提供的FPID和PID功能塊來實現PID控制。2、ADAM-5510KW對可以使用的PID控制回路并無限制，實際上，取決于Scan rate，Scanrate越低，則允許的PID回路越多。3、在實際應用中，流量、液位、壓力、溫度等等對象都可以進行控制。對于流量、液位、壓力等等參數可以用傳感器或變送器轉換為電壓/電流信號接入模擬量輸入模塊ADAM-5017進行采集；對于溫度可以用熱電偶模塊ADAM-5018或熱電阻模塊ADAM-5013進行采集；輸出的執行機構例如調節閥、風扇等等可由模擬量輸出模塊ADAM-5024進行控制。二、 ADAM-5510KW中如何調用FPID/PID功能塊1、FPID功能塊在ProconOS.fwl庫中，先將庫添加進Project中。
上傳時間： 2013-10-12
上傳用戶：it男一枚
Logger iButton devices have gained a lot of popularity with researchers. Although free evaluation software is easy to use and welldocumented, the choices and inputs that need to be made can sometimes be challenging. This application note explains technicalterms that are common with temperature logger iButtons and how they relate to each other. Additionally, it presents an algorithm tohelp users choose the necessary input parameters, including the sample rate based on a user's needs and the available memory tostore the data.
上傳時間： 2013-11-16
上傳用戶：xywhw1
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上傳時間： 2013-12-25
上傳用戶：jkhjkh1982
S3C44BOX的BIOS。可使用的命令：help --- show help ? --- = help date --- show or set current date time --- show or set current time setweek --- set weekday clock --- show system running clock setmclk --- set system running clock setbaud ------ set baud rate ipcfg ------ show or set IP address load ------ load file to ram comload ------ load file from serial port run ------ run from sdram prog ------ program flash copy ------ copy flash from src to dst address boot ------ boot from flash backup ------ move bios to the top of flash md ------ show memory data move ------ move program from flash to sdram
上傳時間： 2015-01-22
上傳用戶：ANRAN
This model simulates a CDMA2000 1xRTT Forward link (between Base Station and Mobile Station). In particular, it simulates the Radio Configuration 3 of a Forward Fundamental channel. The block CDMA2k: Initial settings allows you to set different parameters such as data rate, Power Control SubChannel insertion rate, spreading code index, QOSF index and the channel model.
標簽： Station simulates Forward between
上傳時間： 2015-03-28
上傳用戶：13215175592
This an adaptive receiver for a direct-sequence spread spectrum (DS-SS) system over an AWGN channel. The adaptive receiver block is modified from the LMS adaptive filter block in DSP Blockset. For DS-SS signal reception, the adaptive filter needs to have multi-rate operation. The input sample rate is equal to chip rate and the output is at symbol rate. Two rates are related by PG, processing gain
標簽： direct-sequence adaptive receiver spectrum
上傳時間： 2014-01-16
上傳用戶：D&L37
