BGA布線指南 BGA CHIP PLACEMENT AND routing RULE BGA是PCB上常用的組件，通常CPU、NORTH BRIDGE、SOUTH BRIDGE、AGP CHIP、CARD BUS CHIP…等，大多是以bga的型式包裝，簡(jiǎn)言之，80﹪的高頻信號(hào)及特殊信號(hào)將會(huì)由這類型的package內(nèi)拉出。因此，如何處理BGA package的走線，對(duì)重要信號(hào)會(huì)有很大的影響。 通常環(huán)繞在BGA附近的小零件，依重要性為優(yōu)先級(jí)可分為幾類： 1. by pass。 2. clock終端RC電路。 3. damping（以串接電阻、排組型式出現(xiàn)；例如memory BUS信號(hào)） 4. EMI RC電路（以dampin、C、pull height型式出現(xiàn)；例如USB信號(hào)）。 5. 其它特殊電路（依不同的CHIP所加的特殊電路；例如CPU的感溫電路）。 6. 40mil以下小電源電路組（以C、L、R等型式出現(xiàn)；此種電路常出現(xiàn)在AGP CHIP or含AGP功能之CHIP附近，透過R、L分隔出不同的電源組）。 7. pull low R、C。 8. 一般小電路組（以R、C、Q、U等型式出現(xiàn)；無走線要求）。 9. pull height R、RP。 中文DOC，共5頁，圖文并茂
上傳時(shí)間： 2013-04-24
上傳用戶：cxy9698
Many CAD users dismiss schematic capture as a necessary evil in the process of creating\r\nPCB layout but we have always disputed this point of view. With PCB layout now offering\r\nautomation of both component placement and track routing, getting the des
標(biāo)簽： schematic necessary creating dismiss
上傳時(shí)間： 2013-09-25
上傳用戶：baiom
EDA （Electronic Design Automation）即“電子設(shè)計(jì)自動(dòng)化”，是指以計(jì)算機(jī)為工作平臺(tái)，以EDA軟件為開發(fā)環(huán)境，以硬件描述語言為設(shè)計(jì)語言，以可編程器件PLD為實(shí)驗(yàn)載體(包括CPLD、FPGA、EPLD等)，以集成電路芯片為目標(biāo)器件的電子產(chǎn)品自動(dòng)化設(shè)計(jì)過程。“工欲善其事，必先利其器”，因此，EDA工具在電子系統(tǒng)設(shè)計(jì)中所占的份量越來越高。下面就介紹一些目前較為流行的EDA工具軟件。 PLD 及IC設(shè)計(jì)開發(fā)領(lǐng)域的EDA工具，一般至少要包含仿真器（Simulator）、綜合器（Synthesizer）和配置器（Place and routing, P&R）等幾個(gè)特殊的軟件包中的一個(gè)或多個(gè)，因此這一領(lǐng)域的EDA工具就不包括Protel、PSpice、Ewb等原理圖和PCB板設(shè)計(jì)及電路仿真軟件。目前流行的EDA工具軟件有兩種分類方法：一種是按公司類別進(jìn)行分類，另一種是按功能進(jìn)行劃分。 若按公司類別分，大體可分兩類：一類是EDA 專業(yè)軟件公司，業(yè)內(nèi)最著名的三家公司是Cadence、Synopsys和Mentor Graphics；另一類是PLD器件廠商為了銷售其產(chǎn)品而開發(fā)的EDA工具，較著名的公司有Altera、Xilinx、lattice等。前者獨(dú)立于半導(dǎo)體器件廠商，具有良好的標(biāo)準(zhǔn)化和兼容性，適合于學(xué)術(shù)研究單位使用，但系統(tǒng)復(fù)雜、難于掌握且價(jià)格昂貴；后者能針對(duì)自己器件的工藝特點(diǎn)作出優(yōu)化設(shè)計(jì)，提高資源利用率，降低功耗，改善性能，比較適合產(chǎn)品開發(fā)單位使用。 若按功能分，大體可以分為以下三類。 (1) 集成的PLD/FPGA開發(fā)環(huán)境 由半導(dǎo)體公司提供，基本上可以完成從設(shè)計(jì)輸入（原理圖或HDL）→仿真→綜合→布線→下載到器件等囊括所有PLD開發(fā)流程的所有工作。如Altera公司的MaxplusⅡ、QuartusⅡ，Xilinx公司的ISE，Lattice公司的 ispDesignExpert等。其優(yōu)勢(shì)是功能全集成化，可以加快動(dòng)態(tài)調(diào)試，縮短開發(fā)周期；缺點(diǎn)是在綜合和仿真環(huán)節(jié)與專業(yè)的軟件相比，都不是非常優(yōu)秀的。 (2) 綜合類 這類軟件的功能是對(duì)設(shè)計(jì)輸入進(jìn)行邏輯分析、綜合和優(yōu)化，將硬件描述語句（通常是系統(tǒng)級(jí)的行為描述語句）翻譯成最基本的與或非門的連接關(guān)系（網(wǎng)表），導(dǎo)出給PLD/FPGA廠家的軟件進(jìn)行布局和布線。為了優(yōu)化結(jié)果，在進(jìn)行較復(fù)雜的設(shè)計(jì)時(shí)，基本上都使用這些專業(yè)的邏輯綜合軟件，而不采用廠家提供的集成PLD/FPGA開發(fā)工具。如Synplicity公司的Synplify、Synopsys公司的FPGAexpress、FPGA Compiler Ⅱ等。 (3) 仿真類 這類軟件的功能是對(duì)設(shè)計(jì)進(jìn)行模擬仿真，包括布局布線（P&R）前的“功能仿真”（也叫“前仿真”）和P&R后的包含了門延時(shí)、線延時(shí)等的“時(shí)序仿真”（也叫“后仿真”）。復(fù)雜一些的設(shè)計(jì)，一般需要使用這些專業(yè)的仿真軟件。因?yàn)橥瑯拥脑O(shè)計(jì)輸入，專業(yè)軟件的仿真速度比集成環(huán)境的速度快得多。此類軟件最著名的要算Model Technology公司的Modelsim，Cadence公司的NC-Verilog/NC-VHDL/NC-SIM等。 以上介紹了一些具代表性的EDA 工具軟件。它們?cè)谛阅苌细饔兴L(zhǎng)，有的綜合優(yōu)化能力突出，有的仿真模擬功能強(qiáng)，好在多數(shù)工具能相互兼容，具有互操作性。比如Altera公司的 QuartusII集成開發(fā)工具，就支持多種第三方的EDA軟件，用戶可以在QuartusII軟件中通過設(shè)置直接調(diào)用Modelsim和 Synplify進(jìn)行仿真和綜合。 如果設(shè)計(jì)的硬件系統(tǒng)不是很大，對(duì)綜合和仿真的要求不是很高，那么可以在一個(gè)集成的開發(fā)環(huán)境中完成整個(gè)設(shè)計(jì)流程。如果要進(jìn)行復(fù)雜系統(tǒng)的設(shè)計(jì)，則常規(guī)的方法是多種EDA工具協(xié)調(diào)工作，集各家之所長(zhǎng)來完成設(shè)計(jì)流程。
上傳時(shí)間： 2013-11-19
上傳用戶：wxqman
LAYOUT REPORT .............. 1 目錄.................. 1 1. PCB LAYOUT 術(shù)語解釋(TERMS)......... 2 2. Test Point : ATE 測(cè)試點(diǎn)供工廠ICT 測(cè)試治具使用............ 2 3. 基準(zhǔn)點(diǎn) (光學(xué)點(diǎn)) -for SMD:........... 4 4. 標(biāo)記 (LABEL ING)......... 5 5. VIA HOLE PAD................. 5 6. PCB Layer 排列方式...... 5 7.零件佈置注意事項(xiàng) (PLACEMENT NOTES)............... 5 8. PCB LAYOUT 設(shè)計(jì)............ 6 9. Transmission Line ( 傳輸線 )..... 8 10.General Guidelines – 跨Plane.. 8 11. General Guidelines – 繞線....... 9 12. General Guidelines – Damping Resistor. 10 13. General Guidelines - RJ45 to Transformer................. 10 14. Clock routing Guideline........... 12 15. OSC & CRYSTAL Guideline........... 12 16. CPU
上傳時(shí)間： 2013-12-20
上傳用戶：康郎
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-15
上傳用戶：busterman
The LTM8020, LTM8021, LTM8022 and LTM8023 μModule®regulators are complete easy-to-use encapsulated stepdownDC/DC regulators intended to take the pain and aggravationout of implementing a switching power supplyonto a system board. With a μModule regulator, you onlyneed an input cap, output cap and one or two resistorsto complete the design. As one might imagine, this highlevel of integration greatly simplifi es the task of printedcircuit board design, reducing the effort to four categories:component footprint generation, component placement,routing the nets, and thermal vias.
上傳時(shí)間： 2014-01-18
上傳用戶：laomv123
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
在車載自組網(wǎng)中，路由協(xié)議很大程度上決定了整個(gè)網(wǎng)絡(luò)的性能。如何有效的利用車流信息提高傳輸質(zhì)量是改善路由性能的一個(gè)關(guān)鍵問題。本文基于速度-密度線性模型，提出了一種實(shí)時(shí)車流密度的路由協(xié)議RVDR（Real-time Vehicle Density routing）。該協(xié)議通過與鄰居節(jié)點(diǎn)交換的速度信息，對(duì)相關(guān)道路車流密度進(jìn)行預(yù)測(cè)，并給出基于車流密度信息的路徑選擇方法。仿真結(jié)果表明，與現(xiàn)有協(xié)議相比，RVDR協(xié)議在實(shí)時(shí)性和高效性等性能方面得到改進(jìn)。
上傳時(shí)間： 2014-07-10
上傳用戶：ZJX5201314
很多不同的廠家生產(chǎn)各種型號(hào)的計(jì)算機(jī)，它們運(yùn)行完全不同的操作系統(tǒng)，但TCP.IP協(xié)議族允許它們互相進(jìn)行通信。這一點(diǎn)很讓人感到吃驚，因?yàn)樗淖饔靡堰h(yuǎn)遠(yuǎn)超出了起初的設(shè)想。T C P / I P起源于6 0年代末美國(guó)政府資助的一個(gè)分組交換網(wǎng)絡(luò)研究項(xiàng)目，到9 0年代已發(fā)展成為計(jì)算機(jī)之間最常應(yīng)用的組網(wǎng)形式。它是一個(gè)真正的開放系統(tǒng)，因?yàn)閰f(xié)議族的定義及其多種實(shí)現(xiàn)可以不用花錢或花很少的錢就可以公開地得到。它成為被稱作“全球互聯(lián)網(wǎng)”或“因特網(wǎng)(Internet)”的基礎(chǔ)，該廣域網(wǎng)（WA N）已包含超過1 0 0萬臺(tái)遍布世界各地的計(jì)算機(jī)。本章主要對(duì)T C P / I P協(xié)議族進(jìn)行概述，其目的是為本書其余章節(jié)提供充分的背景知識(shí)。 TCP.IP協(xié)議 縮略語 ACK (ACKnowledgment) TCP首部中的確認(rèn)標(biāo)志 API (Application Programming Interface) 應(yīng)用編程接口 ARP (Address Resolution Protocol) 地址解析協(xié)議 ARPANET(Defense Advanced Research Project Agency NETwork) (美國(guó))國(guó)防部遠(yuǎn)景研究規(guī)劃局 AS (Autonomous System) 自治系統(tǒng) ASCII (American Standard Code for Information Interchange) 美國(guó)信息交換標(biāo)準(zhǔn)碼 ASN.1 (Abstract Syntax Notation One) 抽象語法記法1 BER (Basic Encoding Rule) 基本編碼規(guī)則 BGP (Border Gateway Protocol) 邊界網(wǎng)關(guān)協(xié)議 BIND (Berkeley Internet Name Domain) 伯克利I n t e r n e t域名 BOOTP (BOOTstrap Protocol) 引導(dǎo)程序協(xié)議 BPF (BSD Packet Filter) BSD 分組過濾器 CIDR (Classless InterDomain routing) 無類型域間選路 CIX (Commercial Internet Exchange) 商業(yè)互聯(lián)網(wǎng)交換 CLNP (ConnectionLess Network Protocol) 無連接網(wǎng)絡(luò)協(xié)議 CRC (Cyclic Redundancy Check) 循環(huán)冗余檢驗(yàn) CSLIP (Compressed SLIP) 壓縮的S L I P CSMA (Carrier Sense Multiple Access) 載波偵聽多路存取 DCE (Data Circuit-terminating Equipment) 數(shù)據(jù)電路端接設(shè)備 DDN (Defense Data Network) 國(guó)防數(shù)據(jù)網(wǎng) DF (Don’t Fragment) IP首部中的不分片標(biāo)志 DHCP (Dynamic Host Configuration Protocol) 動(dòng)態(tài)主機(jī)配置協(xié)議 DLPI (Data Link Provider Interface) 數(shù)據(jù)鏈路提供者接口 DNS (Domain Name System) 域名系統(tǒng) DSAP (Destination Service Access Point) 目的服務(wù)訪問點(diǎn) DSLAM (DSL Access Multiplexer) 數(shù)字用戶線接入復(fù)用器 DSSS (Direct Sequence Spread Spectrum) 直接序列擴(kuò)頻 DTS (Distributed Time Service) 分布式時(shí)間服務(wù) DVMRP (Distance Vector Multicast routing Protocol) 距離向量多播選路協(xié)議 EBONE (European IP BackbONE) 歐洲I P主干網(wǎng) EOL (End of Option List) 選項(xiàng)清單結(jié)束 EGP (External Gateway Protocol) 外部網(wǎng)關(guān)協(xié)議 EIA (Electronic Industries Association) 美國(guó)電子工業(yè)協(xié)會(huì) FCS (Frame Check Sequence) 幀檢驗(yàn)序列 FDDI (Fiber Distributed Data Interface) 光纖分布式數(shù)據(jù)接口 FIFO (First In, First Out) 先進(jìn)先出 FIN (FINish) TCP首部中的結(jié)束標(biāo)志 FQDN (Full Qualified Domain Name) 完全合格的域名 FTP (File Transfer Protocol) 文件傳送協(xié)議 HDLC (High-level Data Link Control) 高級(jí)數(shù)據(jù)鏈路控制 HELLO 選路協(xié)議 IAB (Internet Architecture Board) Internet體系結(jié)構(gòu)委員會(huì) IANA (Internet Assigned Numbers Authority) Internet號(hào)分配機(jī)構(gòu) ICMP (Internet Control Message Protocol) Internet控制報(bào)文協(xié)議 IDRP (InterDomain routing Protocol) 域間選路協(xié)議 IEEE (Institute of Electrical and Electronics Engineering) （美國(guó)）電氣與電子工程師協(xié)會(huì) IEN (Internet Experiment Notes) 互聯(lián)網(wǎng)試驗(yàn)注釋 IESG (Internet Engineering Steering Group) Internet工程指導(dǎo)小組 IETF (Internet Engineering Task Force) Internet工程專門小組 IGMP (Internet Group Management Protocol) Internet組管理協(xié)議 IGP (Interior Gateway Protocol) 內(nèi)部網(wǎng)關(guān)協(xié)議 IMAP (Internet Message Access Protocol) Internet報(bào)文存取協(xié)議 IP (Internet Protocol) 網(wǎng)際協(xié)議 I RTF (Internet Research Task Force) Internet研究專門小組 IS-IS (Intermediate System to Intermediate System Protocol) 中間系統(tǒng)到中間系統(tǒng)協(xié)議 ISN (Initial Sequence Number) 初始序號(hào) ISO (International Organization for Standardization) 國(guó)際標(biāo)準(zhǔn)化組織 ISOC (Internet SOCiety) Internet協(xié)會(huì) LAN (Local Area Network) 局域網(wǎng) LBX (Low Bandwidth X) 低帶寬X LCP (Link Control Protocol) 鏈路控制協(xié)議 LFN (Long Fat Net) 長(zhǎng)肥網(wǎng)絡(luò) LIFO (Last In, First Out) 后進(jìn)先出 LLC (Logical Link Control) 邏輯鏈路控制 LSRR (Loose Source and Record Route) 寬松的源站及記錄路由 MBONE (Multicast Backbone On the InterNEt) Internet上的多播主干網(wǎng) MIB (Management Information Base) 管理信息庫 MILNET (MILitary NETwork) 軍用網(wǎng) MIME (Multipurpose Internet Mail Extensions) 通用I n t e r n e t郵件擴(kuò)充 MSL (Maximum Segment Lifetime) 報(bào)文段最大生存時(shí)間 MSS (Maximum Segment Size) 最大報(bào)文段長(zhǎng)度 M TA (Message Transfer Agent) 報(bào)文傳送代理 MTU (Maximum Transmission Unit) 最大傳輸單元 NCP (Network Control Protocol) 網(wǎng)絡(luò)控制協(xié)議 NFS (Network File System) 網(wǎng)絡(luò)文件系統(tǒng) NIC (Network Information Center) 網(wǎng)絡(luò)信息中心 NIT (Network Interface Tap) 網(wǎng)絡(luò)接口栓（S u n公司的一個(gè)程序） NNTP (Network News Transfer Protocol) 網(wǎng)絡(luò)新聞傳送協(xié)議 NOAO (National Optical Astronomy Observatories) 國(guó)家光學(xué)天文臺(tái) NOP (No Operation) 無操作 NSFNET (National Science Foundation NETwork) 國(guó)家科學(xué)基金網(wǎng)絡(luò) NSI (NASA Science Internet) （美國(guó)）國(guó)家宇航局I n t e r n e t NTP (Network Time Protocol) 網(wǎng)絡(luò)時(shí)間協(xié)議 NVT (Network Virtual Terminal) 網(wǎng)絡(luò)虛擬終端 OSF (Open Software Foudation) 開放軟件基金 OSI (Open Systems Interconnection) 開放系統(tǒng)互連 OSPF (Open Shortest Path First) 開放最短通路優(yōu)先 PAWS (Protection Against Wrapped Sequence number) 防止回繞的序號(hào) PDU (Protocol Data Unit) 協(xié)議數(shù)據(jù)單元 POSIX (Portable Operating System Interface) 可移植操作系統(tǒng)接口 PPP (Point-to-Point Protocol) 點(diǎn)對(duì)點(diǎn)協(xié)議 PSH (PuSH) TCP首部中的急迫標(biāo)志 RARP (Reverse Address Resolution Protocol) 逆地址解析協(xié)議 RFC (Request For Comments) Internet的文檔，其中的少部分成為標(biāo)準(zhǔn)文檔 RIP (routing Information Protocol) 路由信息協(xié)議 RPC (Remote Procedure Call) 遠(yuǎn)程過程調(diào)用 RR (Resource Record) 資源記錄 RST (ReSeT) TCP首部中的復(fù)位標(biāo)志 RTO (Retransmission Time Out) 重傳超時(shí) RTT (Round-Trip Time) 往返時(shí)間 SACK (Selective ACKnowledgment) 有選擇的確認(rèn) SLIP (Serial Line Internet Protocol) 串行線路I n t e r n e t協(xié)議 SMI (Structure of Management Information) 管理信息結(jié)構(gòu) SMTP (Simple Mail Transfer Protocol) 簡(jiǎn)單郵件傳送協(xié)議 SNMP (Simple Network Management Protocol) 簡(jiǎn)單網(wǎng)絡(luò)管理協(xié)議 SSAP (Source Service Access Point) 源服務(wù)訪問點(diǎn) SSRR (Strict Source and Record Route) 嚴(yán)格的源站及記錄路由 SWS (Silly Window Syndrome) 糊涂窗口綜合癥 SYN (SYNchronous) TCP首部中的同步序號(hào)標(biāo)志 TCP (Transmission Control Protocol) 傳輸控制協(xié)議 TFTP (Trivial File Transfer Protocol) 簡(jiǎn)單文件傳送協(xié)議 TLI (Transport Layer Interface) 運(yùn)輸層接口 TTL (Ti m e - To-Live) 生存時(shí)間或壽命 TUBA (TCP and UDP with Bigger Addresses) 具有更長(zhǎng)地址的T C P和U D P Telnet 遠(yuǎn)程終端協(xié)議 UA (User Agent) 用戶代理 UDP (User Datagram Protocol) 用戶數(shù)據(jù)報(bào)協(xié)議 URG (URGent) TCP首部中的緊急指針標(biāo)志 UTC (Coordinated Universal Time) 協(xié)調(diào)的統(tǒng)一時(shí)間 UUCP (Unix-to-Unix CoPy) Unix到U n i x的復(fù)制 WAN (Wide Area Network) 廣域網(wǎng) WWW (World Wide Web) 萬維網(wǎng) XDR (eXternal Data Representation) 外部數(shù)據(jù)表示 XID (transaction ID) 事務(wù)標(biāo)識(shí)符 XTI (X/Open Transport Layer Interface) X/ O p e n運(yùn)輸層接口
上傳時(shí)間： 2013-11-13
上傳用戶：tdyoung
為滿足無線網(wǎng)絡(luò)技術(shù)具有低功耗、節(jié)點(diǎn)體積小、網(wǎng)絡(luò)容量大、網(wǎng)絡(luò)傳輸可靠等技術(shù)要求，設(shè)計(jì)了一種以MSP430單片機(jī)和CC2420射頻收發(fā)器組成的無線傳感節(jié)點(diǎn)。通過分析其節(jié)點(diǎn)組成，提出了ZigBee技術(shù)中的幾種網(wǎng)絡(luò)拓?fù)湫问剑⒀芯苛薢igBee路由算法。針對(duì)不同的傳輸要求形式選用不同的網(wǎng)絡(luò)拓?fù)湫问娇梢员M大可能地減少系統(tǒng)成本。同時(shí)針對(duì)不同網(wǎng)絡(luò)選用正確的ZigBee路由算法有效地減少了網(wǎng)絡(luò)能量消耗，提高了系統(tǒng)的可靠性。應(yīng)用試驗(yàn)表明，采用ZigBee方式通信可以提高傳輸速率且覆蓋范圍大，與傳統(tǒng)的有線通信方式相比可以節(jié)約40%左右的成本。 Abstract: To improve the proposed technical requirements such as low-ower， small nodes， large capacity and reliable network transmission， wireless sensor nodes based on MSP430 MCU and CC2420 RF transceiver were designed. This paper provided network topology of ZigBee technology by analysing the component of the nodes and researched ZigBee routing algorithm. Aiming at different requirements of transmission mode to choose the different network topologies form can most likely reduce the system cost. And aiming at different network to choose the correct ZigBee routing algorithm can effectively reduced the network energy consumption and improved the reliability of the system. Results show that the communication which used ZigBee mode can improve the transmission rate， cover more area and reduce 40% cost compared with traditional wired communications mode.
標(biāo)簽： ZigBee 無線傳感網(wǎng)絡(luò) 協(xié)議研究 路由
上傳時(shí)間： 2013-10-09
上傳用戶：robter
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