為Delphi2005做了改動 DSPack 2.3.3 (Sep 2004). DSPack is a set of Components and class to write Multimedia Applications using MS Direct sHow and DirectX technologies. DSPack is designed to work with DirectX 9 on Win9X, ME, 2000, and Windows XP operating systems. Now VMR (Video Mixing Renderer) is available on all Windows Operating Systems. DSPack 2 is designed to work with Delphi 5,6,7 and CPP Builder 6.
標(biāo)簽： DSPack Components Multimedia Delphi
上傳時間： 2014-01-22
上傳用戶：hzy5825468
This article is a very simple introduction writing a Windows Form application for the Microsoft.NET framework using C#. The sample application demonstrates how to create and layout controls on a simple form and the handling of mouse click events. The application displays a form sHowing attributes of a file. This form is similar to the properties dialog box of a file (Right click on a file and Click on Properties menu item). Since attributes of a file will be sHown, the sample will sHow how to use File IO operations in .NET framework.
標(biāo)簽： introduction application Microsoft article
上傳時間： 2015-04-09
上傳用戶：www240697738
This Delphi 4.0 example uses the MapX Ver 4.0 OCX Control. The main goal of this example is to sHow the use of the new object editing capabilities in MapX Ver 3.51. The program sHow how to perform functions such as adding a new layer adding lines and points, and editing a layers data.
標(biāo)簽： example 4.0 Control Delphi
上傳時間： 2015-04-10
上傳用戶：lhc9102
This little program sHows how to use COM technology in Win32Asm. When it s run it lets the user freely decide about the presence of the program with the WS_EX_TOOLWINDOW style on the taskbar. The main goal is to sHow the easiest possible example instead of killing people with the details about virtual tables, polymorphism, inheritance and using nested macros etc., etc.
標(biāo)簽： technology program little sHows
上傳時間： 2015-05-03
上傳用戶：kernaling
This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to sHow the PWM output signal on PORT3.0 and PORT3.1 This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series. You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
標(biāo)簽： the Analyzer Compiler project
上傳時間： 2013-12-19
上傳用戶：Yukiseop
This a script for working with short TCP files with several source nodes, sharing a single bottleneck link. It is used to sHow how with proper choice of CIR, marking decreases losses of vulnerable packets (syns etc).
標(biāo)簽： with bottlenec working several
上傳時間： 2015-05-11
上傳用戶：aa17807091
用win32匯編編寫的類木馬的東西，運行后在機子上打開23端口，用telnet登陸，可以運行下列命令： open filename - open the file or program msg message - place message plainly over screen box message - sHow within a messagebox cdopen - to open CDROM drive door cdclose - to close CDROM drive door bye - terminate connection, handles one user at a time kill - terminate sparczerver
上傳時間： 2013-12-12
上傳用戶：wcl168881111111
請設(shè)計程序，使其實現(xiàn)以秒計時的功能。首先定義一個watch類，它有兩個私有變量begin、end分別表示開始時間、結(jié)束時間，有成員函數(shù)start()、stop()、sHow()分別用來設(shè)置開始時間、結(jié)束時間、顯示持續(xù)時間。
標(biāo)簽： 設(shè)計程序
上傳時間： 2013-12-12
上傳用戶：2467478207
關(guān)于FPGA流水線設(shè)計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We sHow how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
This a collection of sample processes that provide examples ranging from how to use a particular BPEL activity such as pick or scope, to more complex examples of processes that invoke external Web services or sHow techniques such as handling multiple start messages.
標(biāo)簽： collection particular processes examples
上傳時間： 2013-12-26
上傳用戶：sunjet
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