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single-chip

  • C8051F020數據手冊

      The C8051F020/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins (C8051F020/2) or 32 digital I/O pins (C8051F021/3). Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.

    標簽: C8051F020 數據手冊

    上傳時間: 2013-11-08

    上傳用戶:lwq11

  • STM8S105xx_中文資料

    STM8S105xx_中文資料:這本數據手冊描述了STM8S105xx基礎型系列單片機的特點、引腳分配、電氣特性、機械特性和訂購信息。 如果需要關于STM8S單片機存儲器、寄存器和外設等的詳細信息,請參考STM8S系列單片機參考手冊(RM0016) 。 如果需要關于內部Flash存儲器的編程、擦除和保護的信息,請參考STM8S閃存編程手冊(PM0051) 。 如果需要關于調試和SWIM(single wire interface module單線接口模塊),請參考STM8SWIM 通信協議和調試模塊用戶手冊(UM0470) 。 如果需要關于STM8 內核的信息,請參考STM8 CPU編程手冊(PM0044) 。

    標簽: STM 105 xx

    上傳時間: 2013-11-03

    上傳用戶:JasonC

  • NCV7356單線CANBUS收發器數據手冊

    The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.

    標簽: CANBUS 7356 NCV 單線

    上傳時間: 2013-10-24

    上傳用戶:s藍莓汁

  • NIOSII用戶定制指令

    With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor

    標簽: NIOSII 用戶 定制 指令

    上傳時間: 2013-11-07

    上傳用戶:swing

  • C51 V8 專業開發工具

    Keil C51 V8 專業開發工具(PK51)   PK51是為8051系列單片機所設計的開發工具,支持所有8051系列衍生產品,,支持帶擴展存儲器和擴展指令集(例如Dallas390/5240/400,Philips 51MX,Analog Devices MicroConverters)的新設備,以及支持很多公司的一流的設備和IP內核,比如Analog Devices, Atmel, Cypress Semiconductor, Dallas Semiconductor, Goal, Hynix, Infineon, Intel, NXP(founded by Philips), OKI, Silicon Labs,SMSC, STMicroeleectronics,Synopsis, TDK, Temic, Texas Instruments,Winbond等。 通過PK51專業級開發工具,可以輕松地了解8051的On-chip peripherals與及其它關鍵特性。 The PK51專業級開發工具包括… l          μVision Ø         集成開發環境 Ø          調試器 Ø         軟件模擬器   l          Keil 8051擴展編譯工具 Ø         AX51宏匯編程序 Ø         ANSI C編譯工具 Ø         LX51 連接器 Ø         OHX51 Object-HEX 轉換器 l          Keil 8051編譯工具 Ø         A51宏匯編程序 Ø         C51 ANSI C編譯工具 Ø         BL51 代碼庫連接器 Ø         OHX51 Object-HEX 轉換器 Ø         OC51 集合目標轉換器   l          目標調試器 Ø         FlashMON51 目標監控器 Ø         MON51目標監控器 Ø         MON390 (Dallas 390)目標監控器 Ø         MONADI (Analog Devices 812)目標監控器 Ø         ISD51 在系統調試   l          RTX51微實時內核   你應該考慮PK51開發工具包,如果你… l          需要用8051系列單片機來開發 l          需要開發 Dallas 390 或者 Philips 51MX代碼 l          需要用C編寫代碼 l          需要一個軟件模擬器或是沒有硬件仿真器 l          需要在單芯片上基于小實時內核創建復雜的應用

    標簽: C51 V8 開發工具

    上傳時間: 2013-10-30

    上傳用戶:yy_cn

  • 接口選擇指南

    LVDS、xECL、CML(低電壓差分信號傳輸、發射級耦合邏輯、電流模式邏輯)………4多點式低電壓差分信號傳輸(M-LVDS) ……………………………………………………8數字隔離器 ………………………………………………………………………………10RS-485/422 …………………………………………………………………………………11RS-232………………………………………………………………………………………13UART(通用異步收發機)…………………………………………………………………16CAN(控制器局域網)……………………………………………………………………18FlatLinkTM 3G ………………………………………………………………………………19SerDes(串行G 比特收發機及LVDS)……………………………………………………20DVI(數字視頻接口)/PanelBusTM ………………………………………………………22TMDS(最小化傳輸差分信號) …………………………………………………………24USB 集線器控制器及外設器件 …………………………………………………………25USB 接口保護 ……………………………………………………………………………26USB 電源管理 ……………………………………………………………………………27PCI Express® ………………………………………………………………………………29PCI 橋接器 …………………………………………………………………………………33卡總線 (CardBus) 電源開關 ………………………………………………………………341394 (FireWire®, 火線®) ……………………………………………………………………36GTLP (Gunning Transceiver Logic Plus,體效應收發機邏輯+) ………………………………39VME(Versa Module Eurocard)總線 ………………………………………………………41時鐘分配電路 ……………………………………………………………………………42交叉參考指南 ……………………………………………………………………………43器件索引 …………………………………………………………………………………47技術支持 …………………………………………………………………………………48 德州儀器(TI)為您提供了完備的接口解決方案,使得您的產品別具一格,并加速了產品面市。憑借著在高速、復合信號電路、系統級芯片 (system-on-a-chip ) 集成以及先進的產品開發工藝方面的技術專長,我們將能為您提供硅芯片、支持工具、軟件和技術文檔,使您能夠按時的完成并將最佳的產品推向市場,同時占據一個具有競爭力的價格。本選擇指南為您提供與下列器件系列有關的設計考慮因素、技術概述、產品組合圖示、參數表以及資源信息:

    標簽: 接口 選擇指南

    上傳時間: 2013-10-21

    上傳用戶:Jerry_Chow

  • 線性低壓差 (LDO) 穩壓器解決方案

    We offer a broad line of high performance low dropout (LDO) linear regulators with fasttransient response, excellent line and load regulation, and very wide input voltage rangefrom 0.9V to 100V. Output currents range from 20mA to 10A, with positive, negative andmultiple output versions available. Many devices offer output voltage operation <0.8V andsome feature operation as low as 0V, even with a single supply. Most are stable with ceramicoutput capacitors. LDO regulators can be applied in virtually any application.

    標簽: LDO 線性 低壓差 穩壓器

    上傳時間: 2013-11-15

    上傳用戶:努力努力再努力

  • 基于SOPC技術的異步串行通信IP核的設計

    介紹了SoPC(System on a Programmable Chip)系統的概念和特點,給出了基于PLB總線的異步串行通信(UART)IP核的硬件設計和實現。通過將設計好的UART IP核集成到SoPC系統中加以驗證,證明了所設計的UART IP核可以正常工作。該設計方案為其他基于SoPC系統IP核的開發提供了一定的參考。

    標簽: SOPC IP核 異步串行通信

    上傳時間: 2013-11-12

    上傳用戶:894448095

  • 差分電路中單端及混合模式S-參數的使用

    Single-Ended and Differential S-Parameters Differential circuits have been important incommunication systems for many years. In the past,differential communication circuits operated at lowfrequencies, where they could be designed andanalyzed using lumped-element models andtechniques. With the frequency of operationincreasing beyond 1GHz, and above 1Gbps fordigital communications, this lumped-elementapproach is no longer valid, because the physicalsize of the circuit approaches the size of awavelength.Distributed models and analysis techniques are nowused instead of lumped-element techniques.Scattering parameters, or S-parameters, have beendeveloped for this purpose [1]. These S-parametersare defined for single-ended networks. S-parameterscan be used to describe differential networks, but astrict definition was not developed until Bockelmanand others addressed this issue [2]. Bockelman’swork also included a study on how to adapt single-ended S-parameters for use with differential circuits[2]. This adaptation, called “mixed-mode S-parameters,” addresses differential and common-mode operation, as well as the conversion betweenthe two modes of operation.This application note will explain the use of single-ended and mixed-mode S-parameters, and the basicconcepts of microwave measurement calibration.

    標簽: 差分電路 單端 模式

    上傳時間: 2014-03-25

    上傳用戶:yyyyyyyyyy

  • LPC1850 Cortex-M3內核微控制器數據手冊

    The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.

    標簽: Cortex-M 1850 LPC 內核微控制器

    上傳時間: 2014-12-31

    上傳用戶:zhuoying119

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