這是一個(gè)Verilog HDL編寫的RISC cpu的程序，該程序共10個(gè)子程序，實(shí)現(xiàn)了簡單的RISC cpu，可供初學(xué)者參考，學(xué)習(xí)硬件描述語言，及設(shè)計(jì)方法。該程序通過了modelsim仿真驗(yàn)證。
標(biāo)簽： Verilog RISC HDL cpu
上傳時(shí)間： 2015-03-26
上傳用戶：qiao8960
The JDOM build system is based on Jakarta Ant, which is a Java building tool originally developed for the Jakarta Tomcat project but now used in many other Apache projects and extended by many developers.
標(biāo)簽： originally developed building Jakarta
上傳時(shí)間： 2014-01-19
上傳用戶：xg262122
Altera recommends the following system configuration: * Pentium II 400 with 512-MB system memory (faster systems give better software performance) * SVGA monitor * CD-ROM drive * One or more of the following I/O ports: - USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit - Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables - Serial port for MasterBlaster communications cable * TCP/IP networking protocol installed * Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP * Internet Explorer 5.0 or later Memory & Disk Space Requirements USB開發(fā)
標(biāo)簽： system configuration recommends following
上傳時(shí)間： 2015-03-27
上傳用戶：13188549192
This an adaptive receiver for a direct-sequence spread spectrum (DS-SS) system over an AWGN channel. The adaptive receiver block is modified from the LMS adaptive filter block in DSP Blockset. For DS-SS signal reception, the adaptive filter needs to have multi-rate operation. The input sample rate is equal to chip rate and the output is at symbol rate. Two rates are related by PG, processing gain
標(biāo)簽： direct-sequence adaptive receiver spectrum
上傳時(shí)間： 2014-01-16
上傳用戶：D&L37
減1計(jì)數(shù)器 一、設(shè)計(jì)要求 用Verilog HDL語言設(shè)計(jì)一個(gè)計(jì)數(shù)器。 要求計(jì)數(shù)器具有異步置位/復(fù)位功能，可以進(jìn)行自增和自減計(jì)數(shù)，其計(jì)數(shù)周期為2^N（N為二進(jìn)制位數(shù)）。 二、設(shè)計(jì)原理 輸入/輸出說明： d：異步置數(shù)數(shù)據(jù)輸入； q：當(dāng)前計(jì)數(shù)器數(shù)據(jù)輸出； clock：時(shí)鐘脈沖； count_en：計(jì)數(shù)器計(jì)數(shù)使能控制（1：計(jì)數(shù)/0：停止計(jì)數(shù)）； updown：計(jì)數(shù)器進(jìn)行自加/自減運(yùn)算控制（1：自加/0：自減）； load_d
標(biāo)簽： Verilog 計(jì)數(shù)器 HDL 減
上傳時(shí)間： 2015-03-28
上傳用戶：zycidjl
operating system concepts sixth edition windows XP updat 操作系統(tǒng)課后答案
標(biāo)簽： operating concepts edition windows
上傳時(shí)間： 2015-03-28
上傳用戶：lps11188
這是一堆verilog的source code.包含許多常用的小電路.還不錯(cuò)用.
上傳時(shí)間： 2015-03-29
上傳用戶：lanwei
加法器（使用verilog編寫的）,雖然簡單，但是這也是學(xué)習(xí)verilog最基礎(chǔ)的東西！希望大家一起學(xué)習(xí)！
上傳時(shí)間： 2013-12-10
上傳用戶：410805624
這是用verilog寫的一個(gè)簡單的處理器，雖然只具有5個(gè)指令，但是可以透過這個(gè)範(fàn)例，來了解到cpu的架構(gòu)，與如何開發(fā)處理器，相信會(huì)有很大的啟發(fā)。
標(biāo)簽： verilog
上傳時(shí)間： 2014-12-08
上傳用戶：ikemada
手機(jī)文件瀏覽程序的另外一個(gè)版本！ SMan is a system utility that manages your UIQ device. It provides functionality which manufacturers did not provide or which are difficult or impossible to do manually. SMan helps keep your UIQ device running in a "healthy" state and, to a certain degree, allows you to customize the system behaviour of your device.
標(biāo)簽： functionality provides manages utility
上傳時(shí)間： 2013-12-09
上傳用戶：獨(dú)孤求源
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