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• JPEG encoder in Verilog免費下載

  資源簡介：JPEG encoder in Verilog

  標簽： encoder Verilog JPEG in

  上傳時間： 2013-12-31

  上傳用戶：龍飛艇

• 完整的JPEG encoder Verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現(xiàn)精簡電路免費下載

  資源簡介：完整的JPEG encoder Verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現(xiàn)精簡電路

  標簽： convolution transection circular encoder

  上傳時間： 2014-01-20

  上傳用戶：waizhang

• Pure hardware JPEG encoder design. Package includes vhdl source code, test bench, detail design docu免費下載

  資源簡介：Pure hardware JPEG encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.

  標簽： design hardware includes encoder

  上傳時間： 2013-12-15

  上傳用戶：王者A

• mining source code written in Verilog免費下載

  資源簡介：mining source code written in Verilog

  標簽： Verilog written mining source

  上傳時間： 2015-05-06

  上傳用戶：asddsd

• TMS DM642 Motion JPEG encoder and decoder免費下載

  資源簡介：TMS DM642 Motion JPEG encoder and decoder

  標簽： encoder decoder Motion JPEG

  上傳時間： 2015-08-14

  上傳用戶：jyycc

• mips prcessor in Verilog and vhdl免費下載

  資源簡介：mips prcessor in Verilog and vhdl

  標簽： prcessor Verilog mips vhdl

  上傳時間： 2015-10-17

  上傳用戶：sxdtlqqjl

• Generic FIFO, writen in Verilog hdl免費下載

  資源簡介：Generic FIFO, writen in Verilog hdl

  標簽： Generic Verilog writen FIFO

  上傳時間： 2016-02-18

  上傳用戶：zwei41

• Base64 encoder in JAVA免費下載

  資源簡介：Base64 encoder in JAVA

  標簽： encoder Base JAVA 64

  上傳時間： 2013-12-16

  上傳用戶：拔絲土豆

• As the source code name, this code is writing in Verilog and also inside the folder there is a c cod免費下載

  資源簡介：As the source code name, this code is writing in Verilog and also inside the folder there is a c code to see the simulation results from Verilog.

  標簽： code the Verilog writing

  上傳時間： 2013-12-27

  上傳用戶：wangdean1101

• x264 encoder in TI ccs.免費下載

  資源簡介：x264 encoder in TI ccs.

  標簽： encoder x264 ccs TI

  上傳時間： 2016-12-09

  上傳用戶：yzhl1988

• Writing Testbenches classic book in Verilog testbench免費下載

  資源簡介：Writing Testbenches classic book in Verilog testbench

  標簽： Testbenches testbench Writing classic

  上傳時間： 2014-08-03

  上傳用戶：ddddddos

• in term project, we will take the baseline JPEG codec in ARM-based platform system as an example to免費下載

  資源簡介：in term project, we will take the baseline JPEG codec in ARM-based platform system as an example to practice the design flow in SoC. We divide the project into three parts, and the goal of each part is described as follow. Part I: Design ...

  標簽： ARM-based baseline platform project

  上傳時間： 2017-02-15

  上傳用戶：363186

• Color space converter in Verilog HDL免費下載

  資源簡介：Color space converter in Verilog HDL

  標簽： converter Verilog Color space

  上傳時間： 2013-12-22

  上傳用戶：Late_Li

• pll in Verilog in the Appendix免費下載

  資源簡介：pll in Verilog in the Appendix

  標簽： Appendix Verilog in pll

  上傳時間： 2017-03-24

  上傳用戶：集美慧

• This is a simple MIPS processor datapath written in Verilog hardware language. You can see the signa免費下載

  資源簡介：This is a simple MIPS processor datapath written in Verilog hardware language. You can see the signals when emulating in signalscan. Compile it with Verilog in linux.

  標簽： processor datapath hardware language

  上傳時間： 2017-04-22

  上傳用戶：磊子226

• Booth multiplier written in Verilog免費下載

  資源簡介：Booth multiplier written in Verilog

  標簽： multiplier written Verilog Booth

  上傳時間： 2017-04-22

  上傳用戶：天涯

• 6 bit wallace reduction in Verilog免費下載

  資源簡介：6 bit wallace reduction in Verilog

  標簽： reduction wallace Verilog bit

  上傳時間： 2017-04-25

  上傳用戶：bcjtao

• introduction to combinational logic in Verilog免費下載

  資源簡介：introduction to combinational logic in Verilog

  標簽： combinational introduction Verilog logic

  上傳時間： 2014-01-08

  上傳用戶：363186

• Design Testbenches in Verilog HDL language.免費下載

  資源簡介：Design Testbenches in Verilog HDL language.

  標簽： Testbenches language Verilog Design

  上傳時間： 2017-05-04

  上傳用戶：zhaiye

• this is a code for DDS in Verilog免費下載

  資源簡介：this is a code for DDS in Verilog

  標簽： Verilog this code DDS

  上傳時間： 2013-12-03

  上傳用戶：sdq_123

• rs encoder in matlab 7,3免費下載

  資源簡介：rs encoder in matlab 7,3

  標簽： encoder matlab rs in

  上傳時間： 2013-12-26

  上傳用戶：liglechongchong

• it is a 4-bit lcd driver written in Verilog .it will work on spartan 3 xilini devices.免費下載

  資源簡介：it is a 4-bit lcd driver written in Verilog .it will work on spartan 3 xilini devices.

  標簽： devices written Verilog spartan

  上傳時間： 2013-12-07

  上傳用戶：hongmo

• it is a analog i/o interface written in Verilog .it will work on spartan 3 xilini devices.免費下載

  資源簡介：it is a analog i/o interface written in Verilog .it will work on spartan 3 xilini devices.

  標簽： interface devices written Verilog

  上傳時間： 2017-05-24

  上傳用戶：cxl274287265

• these files are written in Verilog but i am uploading in text format免費下載

  資源簡介：these files are written in Verilog but i am uploading in text format

  標簽： uploading written Verilog format

  上傳時間： 2017-06-01

  上傳用戶：520

• these files are written in Verilog but i am uploading in text format免費下載

  資源簡介：these files are written in Verilog but i am uploading in text format

  標簽： uploading written Verilog format

  上傳時間： 2013-12-21

  上傳用戶：wfeel

• these files are written in Verilog but i am uploading in text format免費下載

  資源簡介：these files are written in Verilog but i am uploading in text format

  標簽： uploading written Verilog format

  上傳時間： 2017-06-01

  上傳用戶：wys0120

• these files are written in Verilog but i am uploading in text format免費下載

  資源簡介：these files are written in Verilog but i am uploading in text format

  標簽： uploading written Verilog format

  上傳時間： 2014-11-22

  上傳用戶：jyycc

• this contains the impementation of 5 stage superscalar piepline in Verilog免費下載

  資源簡介：this contains the impementation of 5 stage superscalar piepline in Verilog

  標簽： impementation superscalar contains piepline

  上傳時間： 2017-06-20

  上傳用戶：從此走出陰霾

• A First in first out buffer in Verilog免費下載

  資源簡介：A First in first out buffer in Verilog

  標簽： Verilog buffer First first

  上傳時間： 2013-12-18

  上傳用戶：haohaoxuexi

• an up down counter in Verilog免費下載

  資源簡介：an up down counter in Verilog

  標簽： counter Verilog down an

  上傳時間： 2014-01-24

  上傳用戶：趙云興