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• JPEG encoder in Verilog免費(fèi)下載

  資源簡(jiǎn)介：JPEG encoder in Verilog

  標(biāo)簽： encoder Verilog JPEG in

  上傳時(shí)間： 2013-12-31

  上傳用戶：龍飛艇

• 完整的JPEG encoder Verilog code,DCT部分採(cǎi)用1991 IEEE transection paper,利用skew circular convolution來(lái)實(shí)現(xiàn)精簡(jiǎn)電路免費(fèi)下載

  資源簡(jiǎn)介：完整的JPEG encoder Verilog code,DCT部分採(cǎi)用1991 IEEE transection paper,利用skew circular convolution來(lái)實(shí)現(xiàn)精簡(jiǎn)電路

  標(biāo)簽： convolution transection circular encoder

  上傳時(shí)間： 2014-01-20

  上傳用戶：waizhang

• Pure hardware JPEG encoder design. Package includes vhdl source code, test bench, detail design docu免費(fèi)下載

  資源簡(jiǎn)介：Pure hardware JPEG encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.

  標(biāo)簽： design hardware includes encoder

  上傳時(shí)間： 2013-12-15

  上傳用戶：王者A

• mining source code written in Verilog免費(fèi)下載

  資源簡(jiǎn)介：mining source code written in Verilog

  標(biāo)簽： Verilog written mining source

  上傳時(shí)間： 2015-05-06

  上傳用戶：asddsd

• TMS DM642 Motion JPEG encoder and decoder免費(fèi)下載

  資源簡(jiǎn)介：TMS DM642 Motion JPEG encoder and decoder

  標(biāo)簽： encoder decoder Motion JPEG

  上傳時(shí)間： 2015-08-14

  上傳用戶：jyycc

• mips prcessor in Verilog and vhdl免費(fèi)下載

  資源簡(jiǎn)介：mips prcessor in Verilog and vhdl

  標(biāo)簽： prcessor Verilog mips vhdl

  上傳時(shí)間： 2015-10-17

  上傳用戶：sxdtlqqjl

• Generic FIFO, writen in Verilog hdl免費(fèi)下載

  資源簡(jiǎn)介：Generic FIFO, writen in Verilog hdl

  標(biāo)簽： Generic Verilog writen FIFO

  上傳時(shí)間： 2016-02-18

  上傳用戶：zwei41

• Base64 encoder in JAVA免費(fèi)下載

  資源簡(jiǎn)介：Base64 encoder in JAVA

  標(biāo)簽： encoder Base JAVA 64

  上傳時(shí)間： 2013-12-16

  上傳用戶：拔絲土豆

• As the source code name, this code is writing in Verilog and also inside the folder there is a c cod免費(fèi)下載

  資源簡(jiǎn)介：As the source code name, this code is writing in Verilog and also inside the folder there is a c code to see the simulation results from Verilog.

  標(biāo)簽： code the Verilog writing

  上傳時(shí)間： 2013-12-27

  上傳用戶：wangdean1101

• x264 encoder in TI ccs.免費(fèi)下載

  資源簡(jiǎn)介：x264 encoder in TI ccs.

  標(biāo)簽： encoder x264 ccs TI

  上傳時(shí)間： 2016-12-09

  上傳用戶：yzhl1988

• Writing Testbenches classic book in Verilog testbench免費(fèi)下載

  資源簡(jiǎn)介：Writing Testbenches classic book in Verilog testbench

  標(biāo)簽： Testbenches testbench Writing classic

  上傳時(shí)間： 2014-08-03

  上傳用戶：ddddddos

• in term project, we will take the baseline JPEG codec in ARM-based platform system as an example to免費(fèi)下載

  資源簡(jiǎn)介：in term project, we will take the baseline JPEG codec in ARM-based platform system as an example to practice the design flow in SoC. We divide the project into three parts, and the goal of each part is described as follow. Part I: Design ...

  標(biāo)簽： ARM-based baseline platform project

  上傳時(shí)間： 2017-02-15

  上傳用戶：363186

• Color space converter in Verilog HDL免費(fèi)下載

  資源簡(jiǎn)介：Color space converter in Verilog HDL

  標(biāo)簽： converter Verilog Color space

  上傳時(shí)間： 2013-12-22

  上傳用戶：Late_Li

• pll in Verilog in the Appendix免費(fèi)下載

  資源簡(jiǎn)介：pll in Verilog in the Appendix

  標(biāo)簽： Appendix Verilog in pll

  上傳時(shí)間： 2017-03-24

  上傳用戶：集美慧

• This is a simple MIPS processor datapath written in Verilog hardware language. You can see the signa免費(fèi)下載

  資源簡(jiǎn)介：This is a simple MIPS processor datapath written in Verilog hardware language. You can see the signals when emulating in signalscan. Compile it with Verilog in linux.

  標(biāo)簽： processor datapath hardware language

  上傳時(shí)間： 2017-04-22

  上傳用戶：磊子226

• Booth multiplier written in Verilog免費(fèi)下載

  資源簡(jiǎn)介：Booth multiplier written in Verilog

  標(biāo)簽： multiplier written Verilog Booth

  上傳時(shí)間： 2017-04-22

  上傳用戶：天涯

• 6 bit wallace reduction in Verilog免費(fèi)下載

  資源簡(jiǎn)介：6 bit wallace reduction in Verilog

  標(biāo)簽： reduction wallace Verilog bit

  上傳時(shí)間： 2017-04-25

  上傳用戶：bcjtao

• introduction to combinational logic in Verilog免費(fèi)下載

  資源簡(jiǎn)介：introduction to combinational logic in Verilog

  標(biāo)簽： combinational introduction Verilog logic

  上傳時(shí)間： 2014-01-08

  上傳用戶：363186

• Design Testbenches in Verilog HDL language.免費(fèi)下載

  資源簡(jiǎn)介：Design Testbenches in Verilog HDL language.

  標(biāo)簽： Testbenches language Verilog Design

  上傳時(shí)間： 2017-05-04

  上傳用戶：zhaiye

• this is a code for DDS in Verilog免費(fèi)下載

  資源簡(jiǎn)介：this is a code for DDS in Verilog

  標(biāo)簽： Verilog this code DDS

  上傳時(shí)間： 2013-12-03

  上傳用戶：sdq_123

• rs encoder in matlab 7,3免費(fèi)下載

  資源簡(jiǎn)介：rs encoder in matlab 7,3

  標(biāo)簽： encoder matlab rs in

  上傳時(shí)間： 2013-12-26

  上傳用戶：liglechongchong

• it is a 4-bit lcd driver written in Verilog .it will work on spartan 3 xilini devices.免費(fèi)下載

  資源簡(jiǎn)介：it is a 4-bit lcd driver written in Verilog .it will work on spartan 3 xilini devices.

  標(biāo)簽： devices written Verilog spartan

  上傳時(shí)間： 2013-12-07

  上傳用戶：hongmo

• it is a analog i/o interface written in Verilog .it will work on spartan 3 xilini devices.免費(fèi)下載

  資源簡(jiǎn)介：it is a analog i/o interface written in Verilog .it will work on spartan 3 xilini devices.

  標(biāo)簽： interface devices written Verilog

  上傳時(shí)間： 2017-05-24

  上傳用戶：cxl274287265

• these files are written in Verilog but i am uploading in text format免費(fèi)下載

  資源簡(jiǎn)介：these files are written in Verilog but i am uploading in text format

  標(biāo)簽： uploading written Verilog format

  上傳時(shí)間： 2017-06-01

  上傳用戶：520

• these files are written in Verilog but i am uploading in text format免費(fèi)下載

  資源簡(jiǎn)介：these files are written in Verilog but i am uploading in text format

  標(biāo)簽： uploading written Verilog format

  上傳時(shí)間： 2013-12-21

  上傳用戶：wfeel

• these files are written in Verilog but i am uploading in text format免費(fèi)下載

  資源簡(jiǎn)介：these files are written in Verilog but i am uploading in text format

  標(biāo)簽： uploading written Verilog format

  上傳時(shí)間： 2017-06-01

  上傳用戶：wys0120

• these files are written in Verilog but i am uploading in text format免費(fèi)下載

  資源簡(jiǎn)介：these files are written in Verilog but i am uploading in text format

  標(biāo)簽： uploading written Verilog format

  上傳時(shí)間： 2014-11-22

  上傳用戶：jyycc

• this contains the impementation of 5 stage superscalar piepline in Verilog免費(fèi)下載

  資源簡(jiǎn)介：this contains the impementation of 5 stage superscalar piepline in Verilog

  標(biāo)簽： impementation superscalar contains piepline

  上傳時(shí)間： 2017-06-20

  上傳用戶：從此走出陰霾

• A First in first out buffer in Verilog免費(fèi)下載

  資源簡(jiǎn)介：A First in first out buffer in Verilog

  標(biāo)簽： Verilog buffer First first

  上傳時(shí)間： 2013-12-18

  上傳用戶：haohaoxuexi

• an up down counter in Verilog免費(fèi)下載

  資源簡(jiǎn)介：an up down counter in Verilog

  標(biāo)簽： counter Verilog down an

  上傳時(shí)間： 2014-01-24

  上傳用戶：趙云興