Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
針對(duì)嵌入式機(jī)器視覺系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機(jī)。基于對(duì)智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對(duì)國(guó)內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺(tái)，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行，完成圖像獲取與分析，并作出相應(yīng)輸出。
Abstract:
This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
針對(duì)傳統(tǒng)集成電路（ASIC）功能固定、升級(jí)困難等缺點(diǎn)，利用FPGA實(shí)現(xiàn)了擴(kuò)頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實(shí)現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進(jìn)行低通濾波，給出了DQPSK解調(diào)的原理和實(shí)現(xiàn)方法，推導(dǎo)出一種簡(jiǎn)便的引入?仔/4固定相移的實(shí)現(xiàn)方法。采用模塊化的設(shè)計(jì)方法使用VHDL語(yǔ)言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實(shí)現(xiàn)了整個(gè)系統(tǒng)。測(cè)試結(jié)果表明該系統(tǒng)正確實(shí)現(xiàn)了STEL-2000A的核心功能。
Abstract:
To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。
Abstract:
In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
波長(zhǎng)信號(hào)的解調(diào)是實(shí)現(xiàn)光纖光柵傳感網(wǎng)絡(luò)的關(guān)鍵，基于現(xiàn)有的光纖光柵傳感器解調(diào)方法，提出一種基于FPGA的雙匹配光纖光柵解調(diào)方法，此系統(tǒng)是一種高速率、高精度、低成本的解調(diào)系統(tǒng)，并且通過引入雙匹配光柵有效地克服了雙值問題同時(shí)擴(kuò)大了檢測(cè)范圍。分析了光纖光柵的測(cè)溫原理并給出了該方案軟硬件設(shè)計(jì)，綜合考慮系統(tǒng)的解調(diào)精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。
Abstract:
Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
本文利用Verilog HDL 語(yǔ)言自頂向下的設(shè)計(jì)方法設(shè)計(jì)多功能數(shù)字鐘，突出了其作為硬件描述語(yǔ)言的良好的可讀性、可移植性和易理解等優(yōu)點(diǎn)，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應(yīng)用于實(shí)際的數(shù)字鐘顯示中。
關(guān)鍵詞：Verilog HDL；硬件描述語(yǔ)言；FPGA
Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip.
Keywords: Verilog HDL；hardware description language；FPGA
磁芯電感器的諧波失真分析 摘 要：簡(jiǎn)述了改進(jìn)鐵氧體軟磁材料比損耗系數(shù)和磁滯常數(shù)ηB，從而降低總諧波失真THD的歷史過程，分析了諸多因數(shù)對(duì)諧波測(cè)量的影響，提出了磁心性能的調(diào)控方向。 關(guān)鍵詞：比損耗系數(shù)， 磁滯常數(shù)ηB ，直流偏置特性DC-Bias，總諧波失真THD Analysis on THD of the fer rite co res u se d i n i nductancShi Yan Nanjing Finemag Technology Co. Ltd., Nanjing 210033 Abstract: Histrory of decreasing THD by improving the ratio loss coefficient and hysteresis constant of soft magnetic ferrite is briefly narrated. The effect of many factors which affect the harmonic wave testing is analysed. The way of improving the performance of ferrite cores is put forward. Key words: ratio loss coefficient，hysteresis constant，DC-Bias，THD 近年來，變壓器生產(chǎn)廠家和軟磁鐵氧體生產(chǎn)廠家，在電感器和變壓器產(chǎn)品的總諧波失真指標(biāo)控制上，進(jìn)行了深入的探討和廣泛的合作，逐步弄清了一些似是而非的問題。從工藝技術(shù)上采取了不少有效措施，促進(jìn)了質(zhì)量問題的迅速解決。本文將就此熱門話題作一些粗淺探討。 一、 歷史回顧 總諧波失真（Total harmonic distortion） ，簡(jiǎn)稱THD，并不是什么新的概念，早在幾十年前的載波通信技術(shù)中就已有嚴(yán)格要求<1>。1978年郵電部公布的標(biāo)準(zhǔn)YD/Z17－78“載波用鐵氧體罐形磁心”中，規(guī)定了高μQ材料制作的無中心柱配對(duì)罐形磁心詳細(xì)的測(cè)試電路和方法。如圖一電路所示，利用LC組成的150KHz低通濾波器在高電平輸入的情況下測(cè)量磁心產(chǎn)生的非線性失真。這種相對(duì)比較的實(shí)用方法，專用于無中心柱配對(duì)罐形磁心的諧波衰耗測(cè)試。 這種磁心主要用于載波電報(bào)、電話設(shè)備的遙測(cè)振蕩器和線路放大器系統(tǒng)，其非線性失真有很嚴(yán)格的要求。
圖中 ZD —— QF867 型阻容式載頻振蕩器，輸出阻抗 150Ω， Ld47 —— 47KHz 低通濾波器，阻抗 150Ω，阻帶衰耗大于61dB， Lg88 ——并聯(lián)高低通濾波器，阻抗 150Ω，三次諧波衰耗大于61dB Ld88 ——并聯(lián)高低通濾波器，阻抗 150Ω，三次諧波衰耗大于61dB FD —— 30～50KHz 放大器， 阻抗 150Ω， 增益不小于 43 dB，三次諧波衰耗b3(0)≥91 dB, DP —— Qp373 選頻電平表，輸入高阻抗， L ——被測(cè)無心罐形磁心及線圈， C ——聚苯乙烯薄膜電容器CMO-100V-707APF±0.5%,二只。
測(cè)量時(shí)，所配用線圈應(yīng)用絲包銅電磁線SQJ9×0.12(JB661-75)在直徑為16.1mm的線架上繞制 120 匝， （線架為一格） ， 其空心電感值為 318μH（誤差1％） 被測(cè)磁心配對(duì)安裝好后，先調(diào)節(jié)振蕩器頻率為 36.6～40KHz， 使輸出電平值為+17.4 dB， 即選頻表在 22′端子測(cè)得的主波電平 （P2）為+17.4 dB，然后在33′端子處測(cè)得輸出的三次諧波電平（P3）， 則三次諧波衰耗值為：b3(+2)= P2+S+ P3 式中：S 為放大器增益dB 從以往的資料引證， 就可以發(fā)現(xiàn)諧波失真的測(cè)量是一項(xiàng)很精細(xì)的工作，其中測(cè)量系統(tǒng)的高、低通濾波器，信號(hào)源和放大器本身的三次諧波衰耗控制很嚴(yán)，阻抗必須匹配，薄膜電容器的非線性也有相應(yīng)要求。濾波器的電感全由不帶任何磁介質(zhì)的大空心線圈繞成，以保證本身的“潔凈” ，不至于造成對(duì)磁心分選的誤判。 為了滿足多路通信整機(jī)的小型化和穩(wěn)定性要求， 必須生產(chǎn)低損耗高穩(wěn)定磁心。上世紀(jì) 70 年代初，1409 所和四機(jī)部、郵電部各廠，從工藝上改變了推板空氣窯燒結(jié)，出窯后經(jīng)真空罐冷卻的落后方式，改用真空爐，并控制燒結(jié)、冷卻氣氛。技術(shù)上采用共沉淀法攻關(guān)試制出了μQ乘積 60 萬和 100 萬的低損耗高穩(wěn)定材料，在此基礎(chǔ)上，還實(shí)現(xiàn)了高μ7000～10000材料的突破，從而大大縮短了與國(guó)外企業(yè)的技術(shù)差異。當(dāng)時(shí)正處于通信技術(shù)由FDM（頻率劃分調(diào)制）向PCM（脈沖編碼調(diào)制） 轉(zhuǎn)換時(shí)期， 日本人明石雅夫發(fā)表了μQ乘積125 萬為 0.8×10 ，100KHz）的超優(yōu)鐵氧體材料<3>，其磁滯系數(shù)降為優(yōu)鐵
Integrated EMI/Thermal Design forSwitching Power SuppliesWei ZhangThesis submitted to the Faculty of theVirginia Polytechnic Institute and State Universityin partial fulfillment of the requirements for the degree of
Integrated EMI/Thermal Design forSwitching Power SuppliesWei Zhang(Abstract)This work presents the modeling and analysis of EMI and thermal performancefor switch power supply by using the CAD tools. The methodology and design guidelinesare developed.By using a boost PFC circuit as an example, an equivalent circuit model is builtfor EMI noise prediction and analysis. The parasitic elements of circuit layout andcomponents are extracted analytically or by using CAD tools. Based on the model, circuitlayout and magnetic component design are modified to minimize circuit EMI. EMI filtercan be designed at an early stage without prototype implementation.In the second part, thermal analyses are conducted for the circuit by using thesoftware Flotherm, which includes the mechanism of conduction, convection andradiation. Thermal models are built for the components. Thermal performance of thecircuit and the temperature profile of components are predicted. Improved thermalmanagement and winding arrangement are investigated to reduce temperature.In the third part, several circuit layouts and inductor design examples are checkedfrom both the EMI and thermal point of view. Insightful information is obtained.
Abstract: As industrial control systems (ICSs) have become increasingly connected and use more off-the-shelfcomponents, new vulnerabilities to cyber attacks have emerged. This tutorial looks at three types of ICSs:programmable logic controllers (PLCs), supervisory control and data acquisition (SCADA) systems, anddistributed control systems (DCSs), and then discusses security issues and remedies. This document alsoexplains the benefits and limitations of two cryptographic solutions (digital signatures and encryption) andelaborates on the reasons for using security ICs in an ICS to support cryptography.
