The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上傳時間： 2013-10-24
上傳用戶：s藍莓汁
為滿足無線網絡技術具有低功耗、節點體積小、網絡容量大、網絡傳輸可靠等技術要求，設計了一種以MSP430單片機和CC2420射頻收發器組成的無線傳感節點。通過分析其節點組成，提出了ZigBee技術中的幾種網絡拓撲形式，并研究了ZigBee路由算法。針對不同的傳輸要求形式選用不同的網絡拓撲形式可以盡大可能地減少系統成本。同時針對不同網絡選用正確的ZigBee路由算法有效地減少了網絡能量消耗，提高了系統的可靠性。應用試驗表明，采用ZigBee方式通信可以提高傳輸速率且覆蓋范圍大，與傳統的有線通信方式相比可以節約40%左右的成本。 Abstract: To improve the proposed technical requirements such as low-ower， small nodes， large capacity and reliable network transmission， wireless sensor nodes based on MSP430 MCU and CC2420 RF transceiver were designed. This paper provided network topology of ZigBee technology by analysing the component of the nodes and researched ZigBee routing algorithm. Aiming at different requirements of transmission mode to choose the different network topologies form can most likely reduce the system cost. And aiming at different network to choose the correct ZigBee routing algorithm can effectively reduced the network energy consumption and improved the reliability of the system. Results show that the communication which used ZigBee mode can improve the transmission rate， cover more Area and reduce 40% cost compared with traditional wired communications mode.
上傳時間： 2013-10-09
上傳用戶：robter
通過比較各種隔離數字通信的特點和應用范圍，指出塑料光纖在隔離數字通信中的優勢。使用已經標準化的TOSLINK接口，有利于節省硬件開發成本和簡化設計難度。給出了塑料光纖的硬件驅動電路，說明設計過程中的注意事項，對光收發模塊的電壓特性和頻率特性進行全面試驗，并給出SPI口使用塑料光纖隔離通信的典型應用電路圖。試驗結果表明，該設計可為電力現場、電力電子及儀器儀表的設計提供參考。 Abstract: y comparing characteristics and applications Area of various isolated digital communications， this article indicates advantages of plastic optical fiber in isolated digital communications. Using the standardized TOSLINK interface， it helps to control costs and difficulty in hardware development and design. Then it gives the hardware driver circuit of plastic optical fiber module， explains the noticed details in design process， gives results on the basis of the optical transceiver module voltage characteristics and frequency characteristics tests. Finally，it gives typical application circuit of the SPI communication port by using plastic optical fiber isolation .The results show that this design can be referenced for the power field， power electronics and instrumentation design.
上傳時間： 2014-01-10
上傳用戶：gundan
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and Area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
CAN（Controller Area Network——控制器局域網）是一種由 CAN 控制器組成的高性能串行數據局域通信網絡，是國際上應用最廣泛的現場總線之一。它最早由德國 Bosch 公司于 1984 年推出，最初用于汽車內部測量與執行部件之間的數據通信。CAN-bus 總線模型符合 OSI 的 7 層結構；CAN-bus 規范已被 ISO 估計標準組織制定為國際標準。
上傳時間： 2013-11-13
上傳用戶：lvzhr
Displaying a large bitmap file on a dialog box, in its original size, is quite difficult in the VC++ environment. However, it is possible to display a large bitmap to a predefined Area of the dialog by using the StretchBlt( ) function.The major disadvantage of this is that the clarity of the image will be lost. Check out this article for displaying large bitmaps into the desired Area of your dialog box in its original size with a scrolling technique used to show the entire bitmap. 滾動顯示位圖 在VC++環境下，在一個對話框中顯示一個原始尺寸的大小的位圖文件相當是困難的。然而,通過使用 StretchBlt()函數一個給定的區域顯示一個大的位圖是可能的。主要的缺點是圖像將會失真?？戳诉@篇通過卷動技術顯示整個位圖技術的文章，你將能夠以它的原始尺寸在給定對話框的區域內顯示一個大位圖。 來源: http://www.codeguru.com/bitmap/ScrollBitmap.html
標簽： Displaying difficult original bitmap
上傳時間： 2014-01-05
上傳用戶：yiwen213
一個簡單的詞法分析器，1代表字符，2代表關鍵字（命令字），4帶表算符界符， 注：要把wangs.txt這個文件放在桌面上，然后在這個TXT里寫上你要識別的語句。然后保存后關畢，在運行WANG詞法分析.EXE進行詞法分析。 完成識別后，會在相應的詞面前出現以上代號。暫不能對數字進行識別。因為在某種請況下數字也可表是為字符……稍有困難，但完成老師的針對程序段：Area=b+c*d。那簡直是小菜一碟。
標簽： 分析器
上傳時間： 2013-12-20
上傳用戶：qq21508895
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant Area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
This lab exercise will cover the use of AccelDSP’s design exploration capabilities that include mapping variables to memory and unrolling loop and vector operations. You will learn how to create different hardware architectures without modifying the MATLAB source to explore different Area/performance tradeoffs.
標簽： capabilities exploration AccelDSP exercise
上傳時間： 2014-12-22
上傳用戶：eclipse
In 1960, R.E. Kalman published his famous paper describing a recursive solution to the discrete-data linear filtering problem. Since that time, due in large part to advances in digital computing, the Kalman filter has been the subject of extensive research and application, particularly in the Area of autonomous or assisted navigation.
標簽： R.E. discrete-dat describing published
上傳時間： 2015-10-22
上傳用戶：2404
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