當(dāng)拿到一張CASE單時(shí)，首先得確定的是能用什么母體才能實(shí)現(xiàn)此功能，然后才能展開對(duì)外圍硬件電路的設(shè)計(jì)，因此首先得了解每個(gè)母體的基本功能及特點(diǎn)，下面大至的介紹一下本公司常用的IC：?jiǎn)涡酒鉀Q方案• SN8P1900 系列– 高精度 16-Bit 模數(shù)轉(zhuǎn)換器– 可編程運(yùn)算放大器 (PGIA)• 信號(hào)放大低漂移: 2V• 放大倍數(shù)可編程: 1/16/64/128 倍– 升壓- 穩(wěn)壓調(diào)節(jié)器 (Charge-Pump Regulator)• 電源輸入: 2.4V ~ 5V• 穩(wěn)壓輸出: e.g. 3.8V at SN8P1909– 內(nèi)置液晶驅(qū)動(dòng)電路 (LCD Driver)– 單芯片解決方案 • 耳溫槍 SN8P1909 LQFP 80 Pins• 5000 解析度量測(cè)器 SN8P1908 LQFP 64 Pins• 體重計(jì) SN8P1907 SSOP 48 Pins單芯片解決方案• SN8P1820 系列– 精確的12-Bit 模數(shù)轉(zhuǎn)換器– 可編程運(yùn)算放大器 (PGIA)• Gain Stage One: Low Offset 5V, Gain: 16/32/64/128• Gain Stage One: Low Offset 2mV, Gain: 1.3 ~ 2.5– 升壓- 穩(wěn)壓調(diào)節(jié)器• 電源輸入: 2.4V ~ 5V• 穩(wěn)壓輸出: e.g. 3.8V at SN8P1829– 內(nèi)置可編程運(yùn)算放大電路– 內(nèi)置液晶驅(qū)動(dòng)電路 – 單芯片解決方案 • 電子醫(yī)療器 SN8P1829 LQFP 80 Pins 高速/低功耗/高可靠性微控制器• 最新SN8P2000 系列– SN8P2500/2600/2700 系列– 高度抗交流雜訊能力• 標(biāo)準(zhǔn)瞬間電壓脈沖群測(cè)試 (EFT): IEC 1000-4-4• 雜訊直接灌入芯片電源輸入端• 只需添加1顆 2.2F/50V 旁路電容• 測(cè)試指標(biāo)穩(wěn)超 4000V (歐規(guī))– 高可靠性復(fù)位電路保證系統(tǒng)正常運(yùn)行• 支持外部復(fù)位和內(nèi)部上電復(fù)位• 內(nèi)置1.8V 低電壓偵測(cè)可靠復(fù)位電路• 內(nèi)置看門狗計(jì)時(shí)器保證程序跳飛可靠復(fù)位– 高抗靜電/栓鎖效應(yīng)能力– 芯片工作溫度有所提高: -200C ~ 700C 工規(guī)芯片溫度： -400C ~ 850C 高速/低功耗/高可靠性微控制器• 最新 SN8P2000 系列– SN8P2500/2600/2700 系列– 1T 精簡(jiǎn)指令級(jí)結(jié)構(gòu)• 1T: 一個(gè)外部振蕩周期執(zhí)行一條指令• 工作速度可達(dá)16 MIPS / 16 MHz Crystal– 工作消耗電流 < 2mA at 1-MIPS/5V– 睡眠模式下消耗電流 < 1A / 5V額外功能• 高速脈寬調(diào)制輸出 (PWM)– 8-Bit PWM up to 23 KHz at 12 MHz System Clock– 6-Bit PWM up to 93 KHz at 12 MHz System Clock– 4-Bit PWM up to 375 KHz at 12 MHz System Clock• 內(nèi)置高速16 MHz RC振蕩器 (SN8P2501A)• 電壓變化喚醒功能• 可編程控制沿觸發(fā)/中斷功能– 上升沿 / 下降沿 / 雙沿觸發(fā)• 串行編程接口
標(biāo)簽： 單片機(jī) 線路設(shè)計(jì)
上傳時(shí)間： 2013-10-21
上傳用戶：jiahao131
用單片機(jī)配置FPGA—PLD設(shè)計(jì)技巧 Configuration/Program Method for Altera Device Configure the FLEX Device You can use any Micro-Controller to configure the FLEX device–the main idea is clocking in ONE BITof configuration data per CLOCK–start from the BIT 0The total Configuration time–e.g. 10K10 need 15K byte configuration file•calculation equation–10K10* 1.5= 15Kbyte–configuration time for the file itself•15*1024*8*clock = 122,880Clock•assume the CLOCK is 4MHz•122,880*1/4Mhz=30.72msec
標(biāo)簽： FPGA PLD 用單片機(jī) 設(shè)計(jì)技巧
上傳時(shí)間： 2013-10-09
上傳用戶：a67818601
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時(shí)間： 2013-10-15
上傳用戶：euroford
a8259 可編程中斷控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時(shí)間： 2014-11-29
上傳用戶：zhyiroy
The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/Output (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.
上傳時(shí)間： 2013-10-26
上傳用戶：yuzsu
The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
標(biāo)簽： lpc datasheet 2292 2294
上傳時(shí)間： 2014-12-30
上傳用戶：aysyzxzm
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
上傳時(shí)間： 2013-10-11
上傳用戶：yuchunhai1990
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時(shí)間： 2014-01-17
上傳用戶：Altman
飛思卡爾智能車的舵機(jī)測(cè)試程序 #include <hidef.h> /* common defines and macros */#include <MC9S12XS128.h> /* derivative information */#pragma LINK_INFO DERIVATIVE "mc9s12xs128" void SetBusCLK_16M(void) { CLKSEL=0X00; PLLCTL_PLLON=1; //鎖相環(huán)電路允許位 SYNR=0x00 | 0x01; //SYNR=1 REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK==1)); CLKSEL_PLLSEL =1; } void PWM_01(void) { //舵機(jī)初始化 PWMCTL_CON01=1; //0和1聯(lián)合成16位PWM； PWMCAE_CAE1=0; //選擇輸出模式為左對(duì)齊輸出模式 PWMCNT01 = 0; //計(jì)數(shù)器清零； PWMPOL_PPOL1=1; //先輸出高電平，計(jì)數(shù)到DTY時(shí)，反轉(zhuǎn)電平 PWMPRCLK = 0X40; //clockA 不分頻,clockA=busclock=16MHz;CLK B 16分頻:1Mhz PWMSCLA = 0x08; //對(duì)clock SA 16分頻,pwm clock=clockA/16=1MHz; PWMCLK_PCLK1 = 1; //選擇clock SA做時(shí)鐘源 PWMPER01 = 20000; //周期20ms； 50Hz; PWMDTY01 = 1500; //高電平時(shí)間為1.5ms; PWME_PWME1 = 1;
標(biāo)簽： 飛思卡爾智能車 舵機(jī) 測(cè)試程序
上傳時(shí)間： 2013-11-04
上傳用戶：狗日的日子
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