s3c2410 ads下的測試程序移植到 iar ewarm v5.2；包括 Please select function : 0 : Please input 1-14 to select test 1 : Real time CLOCK display 2 : 4 key array test 3 : Buzzer test 4 : ADC test 5 : IIC EEPROM test 6 : Touchpanel test 7 : 3.5# TFT LCD 240*320 test 8 : UDA1341 play audio test 9 : UDA1341 record audio test 10 : IRDA test 11 : SD Card write and read test 12 : COM port ( UART2 ) test
標簽： Please select function s3c2410
上傳時間： 2016-10-01
上傳用戶：225588
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial CLOCK line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
標簽： bus bidirectional primarily designed
上傳時間： 2013-12-11
上傳用戶：jeffery
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at CLOCK rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2013-12-13
上傳用戶：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at CLOCK rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2014-01-20
上傳用戶：三人用菜
大學計算機操作系統課程設計，完成頁面置換功能，利用CLOCK算法
上傳時間： 2014-02-01
上傳用戶：杜瑩12345
本模擬I2C軟件包包含了I2C操作的底層子程序，使用前要定義 好SCL和SDA。在標準8051模式(12 CLOCK)下,對主頻要求是不高于12MHz(即1個 機器周期1us) 若Fosc>12MHz則要增加相應的NOP指令數。(總線時序符合I2C標 準模式,100Kbit/S)。
上傳時間： 2013-12-08
上傳用戶：ruixue198909
The XC226x derivatives are high-performance members of the Infineon XC2000 Family of full-feature single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 80 million instructions per second) with extended peripheral functionality and enhanced IO capabilities. Optimized peripherals can be adapted flexibly to meet the application requirements. These derivatives utilize CLOCK generation via PLL and internal or external CLOCK sources. Onchip memory modules include program Flash, program RAM, and data RAM.
標簽： high-performance full-feature derivatives Infineon
上傳時間： 2016-12-12
上傳用戶：wab1981
DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital CLOCK Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a CLOCK rate of 133 MHz, 16-bit data changes at both CLOCK edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
利用QuartusII的"MegaWizard Plug-In Manager", 設計輸入數據寬度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它們作為一個project,DEVICE選用EPF10K70RC240-4，對它們進行 時序仿真，將仿真波形（輸入輸出選用group）在一頁紙上打印出來。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER， 設計一個20bit的up_only COUNTER, 要求該COUNTER在FE0FA和FFFFF之間自動循環計數； 分析該COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4幾種芯片中的最大工作頻率； 請將計數器的輸出值在FFFFC--FE0FF之間的仿真波形打印出來 （僅EPF10K70RC240-4芯片,最大允許CLOCK頻率下）。
標簽： MegaWizard QuartusII Manager COMPARE
上傳時間： 2016-12-26
上傳用戶：王者A
595——8位數碼管循環移位顯示.doc │ 利用74HC595實現多位LED顯示的新方法.doc │ 用74HC595芯片驅動LED的電路設計.pdf │ 文件目錄表繪制.cmd │ 文件夾目錄.txt │ 文件名目錄.txt │ ├─點陣設計 │ 74HC595PW.pdf │ 正文點陣設計.doc │ ├─Use595_4(Alexi) │ Use595_2.c │ Use595_4.hex │ Use595_4(Alexi).PWI │ Use595_4(Alexi).DSN │ ├─電子鐘（595） │ ECLOCK_2.hex │ ECLOCK_2.c │ ECLOCK_2.Opt │ ECLOCK_2.Uv2 │ ECLOCK_2_1.hex │ E-CLOCK.DSN │ E-CLOCK.PWI │ └─資料介紹 595.jpg 74HC595真值表.png 74hc595.doc ★595引腳介紹★.doc 74HC595PW.pdf
上傳時間： 2014-01-07
上傳用戶：aa17807091
