s3c2410 ads下的測試程序移植到 iar ewarm v5.2；包括
Please select function :
0 : Please input 1-14 to select test
1 : Real time CLOCK display
2 : 4 key array test
3 : Buzzer test
4 : ADC test
5 : IIC EEPROM test
6 : Touchpanel test
7 : 3.5# TFT LCD 240*320 test
8 : UDA1341 play audio test
9 : UDA1341 record audio test
10 : IRDA test
11 : SD Card write and read test
12 : COM port ( UART2 ) test
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control
and data transfer communication between ICs.
Some of the features of the I2C bus are:
• Two signal lines, a serial data line (SDA) and a serial CLOCK line (SCL), and ground are required. A
12V supply line (500mA max.) for powering the peripherals often may be present.
• Each device connected to the bus is software addressable by a unique address and simple
master/ slave relationships exist at all times masters can operate as master-transmitters or as
master-receivers.
• The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data
corruption if two or more masters simultaneously initiate data transfer systems.
• Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard
mode or up to 400 KBit/s in the fast mode.
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at CLOCK rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at CLOCK rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
The XC226x derivatives are high-performance members of the Infineon XC2000 Family
of full-feature single-chip CMOS microcontrollers. These devices extend the functionality
and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and
speed. They combine high CPU performance (up to 80 million instructions per second)
with extended peripheral functionality and enhanced IO capabilities. Optimized
peripherals can be adapted flexibly to meet the application requirements. These
derivatives utilize CLOCK generation via PLL and internal or external CLOCK sources. Onchip
memory modules include program Flash, program RAM, and data RAM.
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計(jì)文檔。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital CLOCK
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a CLOCK rate of 133 MHz,
16-bit data changes at both CLOCK edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.
