<rt id="44o8i"></rt>
實現產生偽隨機序列的部件 —— 線性反饋移位寄存器單元。 SFlog2為擴頻因子的底數為2的對數值，Cycle為PN序列的周期，其值為2^SFlog2。initial_state為移位寄存器的初始狀態，generator_polynomial_coefficient為生成PN序列所需的本原多項式，對應于移位寄存器的連接向量。
上傳時間： 2016-08-12
上傳用戶：zukfu
The purpose of this document is to present how to use the Timer for the generation of a PWM signal tunable in frequency and duty Cycle. As an application example, this document is based on a basic “music” synthesizer through an external buzzer. Example code is also available in the it.
標簽： generation the document purpose
上傳時間： 2013-12-20
上傳用戶：z754970244
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one Cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2013-12-13
上傳用戶：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one Cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2014-01-20
上傳用戶：三人用菜
完成在tigersharc201平臺上劃分出多個heap的操作，同時示例在多個heap之間切換時的方法，并做出各種內存下訪問的Cycle統計
標簽： tigersharc heap 201 分
上傳時間： 2013-12-24
上傳用戶：壞天使kk
*** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a ** PIC16C54 8-bit CMOS single chip microcomputer ** Revsied Version 2.0 (4/2/92). ** ** Part use = PIC16C54-XT/JW ** Note: 1) All timings are based on a reference crystal frequency of 2MHz ** which is equivalent to an instruction Cycle time of 2 usec. ** 2) Address and literal values are read in octal unless otherwise ** specified.
標簽： Microchip Routines Sample WRITE
上傳時間： 2013-12-27
上傳用戶：ljmwh2000
It contains a vhdl description of the external bus interface unit for 68000 processor. currently only read and write Cycle are supported
標簽： description currently interface processor
上傳時間： 2017-03-16
上傳用戶：chenlong
Edge Disjoint Cycles. You are given an input graph that is either directed or undirected. Write a program that reads in a vertex number and lists the number of edge disjoint Cycles that start and end at this vertex. The output should also list the edges in each of the Cycle discovered. Input will be the adjacency matrix preceded by a 0 or 1 representing Directed or Undirected graphs respectively.
標簽： undirected Disjoint directed Cycles
上傳時間： 2017-04-08
上傳用戶：13188549192
蟻群算法經典TSP模型，ANT-Cycle算法的實現。 使用了C++的STL庫。 原是我畢設的一部分 現在貢獻出來 。 PS:網上能得到的基本上不能直接運行 而我這個復制到vc++6.0的控制臺工程中即可 文件中的文件“oliver30Tsp.dat” 為實現蟻群算法的經典例子，網上還有很多類似的測試例子
上傳時間： 2014-09-01
上傳用戶：Miyuki
This experiment uses the Blackfi n BF533/BF537 EZ-KIT to run a simple FIR fi lter on stereo channels at a sampling frequency of 48 kHz. The Cycle register is embedded in the main program ( process_data.c) to benchmark the time needed to process two FIR fi lters. A background telemetry channel (BTC) is set up to display the Cycle count.
標簽： experiment Blackfi EZ-KIT channe
上傳時間： 2013-12-27
上傳用戶：baiom
<rt id="oiuaw"></rt>
<rt id="oiuaw"></rt>