This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
本文采用Altera公司的FPGA器件Cyclone III系列EP3C10作為核心器件構成了R-S(255,223)編碼系統;利用Quartus II 9.0作為硬件仿真平臺,用硬件描述語言Verilog_HDL實現編程,并且通過JTAG接口與EP3C10連接。R-S(Reed-Solomon)碼是一類糾錯能力很強的特殊的非二進制BCH碼,能應對隨機性和突發性錯誤,廣泛應用于各種通信系統中和保密系統中。R-S(255,223)碼能夠檢測32字節長度和糾錯16字節長度的連續數據錯誤信息。