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HDlC vhdl

HDLC協議RS485總線控制器的FPGA實現

介紹了HDLC協議RS485總線控制器的FPGA實現

標簽： HDLC FPGA 485 RS

上傳時間： 2013-10-18

上傳用戶：zhengjian
用FPGA實現RS485通信接口芯片

在點對多點主從通信系統中,需要合適的接口形式和通信協議實現主站與各從站的信息交換。RS -485 接口是適合這種需求的一種標準接口形式。當選擇主從多點同步通信方式時,工作過程與幀格式符合HDLC/SDLC協議。介紹了采用VHDL 語言在FPGA 上實現的以HDLC/ SDLC 協議控制為基礎的RS - 485 通信接口芯片。實驗表明,這種接口芯片操作簡單、體積小、功耗低、可靠性高,極具實用價值。

標簽： FPGA 485 RS 通信接口

上傳時間： 2014-01-02

上傳用戶：z240529971
The VHDL Cookbook (VHDL編碼書籍)

The VHDL Cookbook是是VHDL編碼書籍。

標簽： VHDL Cookbook The 編碼

上傳時間： 2013-11-19

上傳用戶：lixqiang
US Navy VHDL Modelling Guide

This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.

標簽： Modelling Guide Navy VHDL

上傳時間： 2013-11-20

上傳用戶：pzw421125
PLD Programming Using VHDL

本文詳細討論了VHDL語句對PLD設計的影響和設計經驗，經典文章，值得仔細閱讀消化。,PLD Programming Using VHDL

標簽： Programming Using VHDL PLD

上傳時間： 2013-10-14

上傳用戶：www240697738
VHDL,Verilog,System verilog比較

本文簡單討論并總結了VHDL、Verilog，System verilog 這三中語言的各自特點和區別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

標簽： Verilog verilog System VHDL

上傳時間： 2014-03-03

上傳用戶：zhtzht
基于CPLD的VHDL語言數字鐘(含秒表)設計

利用一塊芯片完成除時鐘源、按鍵、揚聲器和顯示器（數碼管）之外的所有數字電路功能。所有數字邏輯功能都在CPLD器件上用VHDL語言實現。這樣設計具有體積小、設計周期短（設計過程中即可實現時序仿真）、調試方便、故障率低、修改升級容易等特點。本設計采用自頂向下、混合輸入方式（原理圖輸入—頂層文件連接和VHDL語言輸入—各模塊程序設計）實現數字鐘的設計、下載和調試。

標簽： CPLD VHDL 語言數字

上傳時間： 2013-10-24

上傳用戶：古谷仁美
基于FPGA的多通道HDLC通信系統設計與實現

為了滿足某測控平臺的設計要求，設計并實現了基于FPGA的六通道HDLC并行通信系統。該系統以FPGA為核心，包括FPGA、DSP、485轉換接口等部分。給出了系統的電路設計、關鍵模塊及軟件流程圖。測試結果表明，系統通訊速度為1 Mb/s，并且工作穩定，目前該設計已經成功應用于某樣機中。

標簽： FPGA HDLC 多通道通信

上傳時間： 2013-10-12

上傳用戶：as275944189
ZBT SRAM控制器參考設計,xilinx提供VHDL代碼

ZBT SRAM控制器參考設計,xilinx提供VHDL代碼 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.

標簽： xilinx SRAM VHDL ZBT

上傳時間： 2013-10-25

上傳用戶：peterli123456
USB接口控制器參考設計,xilinx提供VHDL代碼 us

USB接口控制器參考設計,xilinx提供VHDL代碼 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

標簽： xilinx VHDL USB us

上傳時間： 2013-10-29

上傳用戶：zhouchang199