Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時(shí)間： 2013-11-21
上傳用戶：不懂夜的黑
The Circuit Designer’s Companion Second edition Tim Williams
標(biāo)簽： Designers Companion Circuit PCB
上傳時(shí)間： 2013-10-08
上傳用戶：sxdtlqqjl
This application note describes how the existing dual-port block memories in the Spartan™-IIand Virtex™ families can be used as Quad-Port memories. This essentially involves a dataaccess time (halved) versus functionality (doubled) trade-off. The overall bandwidth of the blockmemory in terms of bits per second will remain the same.
上傳時(shí)間： 2014-01-24
上傳用戶：15527161163
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.
上傳時(shí)間： 2013-10-21
上傳用戶：ligi201200
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點(diǎn)DSP算法實(shí)現(xiàn)方案： High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
上傳時(shí)間： 2013-10-21
上傳用戶：huql11633
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog Digital Coding
上傳時(shí)間： 2013-11-23
上傳用戶：我干你啊
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時(shí)間： 2013-11-20
上傳用戶：pzw421125
FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development
標(biāo)簽： Methodology Design Reuse FPGA
上傳時(shí)間： 2013-11-01
上傳用戶：shawvi
數(shù)字與模擬電路設(shè)計(jì)技巧IC與LSI的功能大幅提升使得高壓電路與電力電路除外，幾乎所有的電路都是由半導(dǎo)體組件所構(gòu)成，雖然半導(dǎo)體組件高速、高頻化時(shí)會(huì)有EMI的困擾，不過為了充分發(fā)揮半導(dǎo)體組件應(yīng)有的性能，電路板設(shè)計(jì)與封裝技術(shù)仍具有決定性的影響。 模擬與數(shù)字技術(shù)的融合由于IC與LSI半導(dǎo)體本身的高速化，同時(shí)為了使機(jī)器達(dá)到正常動(dòng)作的目的，因此技術(shù)上的跨越競(jìng)爭(zhēng)越來越激烈。雖然構(gòu)成系統(tǒng)的電路未必有clock設(shè)計(jì)，但是毫無疑問的是系統(tǒng)的可靠度是建立在電子組件的選用、封裝技術(shù)、電路設(shè)計(jì)與成本，以及如何防止噪訊的產(chǎn)生與噪訊外漏等綜合考慮。機(jī)器小型化、高速化、多功能化使得低頻/高頻、大功率信號(hào)/小功率信號(hào)、高輸出阻抗/低輸出阻抗、大電流/小電流、模擬/數(shù)字電路，經(jīng)常出現(xiàn)在同一個(gè)高封裝密度電路板，設(shè)計(jì)者身處如此的環(huán)境必需面對(duì)前所未有的設(shè)計(jì)思維挑戰(zhàn)，例如高穩(wěn)定性電路與吵雜(noisy)性電路為鄰時(shí)，如果未將噪訊入侵高穩(wěn)定性電路的對(duì)策視為設(shè)計(jì)重點(diǎn)，事后反復(fù)的設(shè)計(jì)變更往往成為無解的夢(mèng)魘。模擬電路與高速數(shù)字電路混合設(shè)計(jì)也是如此，假設(shè)微小模擬信號(hào)增幅后再將full scale 5V的模擬信號(hào)，利用10bit A/D轉(zhuǎn)換器轉(zhuǎn)換成數(shù)字信號(hào)，由于分割幅寬祇有4.9mV，因此要正確讀取該電壓level并非易事，結(jié)果造成10bit以上的A/D轉(zhuǎn)換器面臨無法順利運(yùn)作的窘境。另一典型實(shí)例是使用示波器量測(cè)某數(shù)字電路基板兩點(diǎn)相隔10cm的ground電位，理論上ground電位應(yīng)該是零，然而實(shí)際上卻可觀測(cè)到4.9mV數(shù)倍甚至數(shù)十倍的脈沖噪訊(pulse noise)，如果該電位差是由模擬與數(shù)字混合電路的grand所造成的話，要測(cè)得4.9 mV的信號(hào)根本是不可能的事情，也就是說為了使模擬與數(shù)字混合電路順利動(dòng)作，必需在封裝與電路設(shè)計(jì)有相對(duì)的對(duì)策，尤其是數(shù)字電路switching時(shí)，ground vance noise不會(huì)入侵analogue ground的防護(hù)對(duì)策，同時(shí)還需充分檢討各電路產(chǎn)生的電流回路(route)與電流大小，依此結(jié)果排除各種可能的干擾因素。以上介紹的實(shí)例都是設(shè)計(jì)模擬與數(shù)字混合電路時(shí)經(jīng)常遇到的瓶頸，如果是設(shè)計(jì)12bit以上A/D轉(zhuǎn)換器時(shí)，它的困難度會(huì)更加復(fù)雜。
標(biāo)簽： 數(shù)字 模擬電路 設(shè)計(jì)技巧
上傳時(shí)間： 2014-02-12
上傳用戶：wenyuoo
UART 4 UART參考設(shè)計(jì)，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
標(biāo)簽： UART Xilinx VHDL 參考設(shè)計(jì)
上傳時(shí)間： 2013-11-02
上傳用戶：18862121743
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