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The PCA9674/74A is a drop-in upgrade for the PCF8574/74A providing higher Fast-modePlus I2C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWMdimming of LEDs, higher I2C-bus drive (30 mA versus 3 mA) so that many more devicescan be on the bus without the need for bus buffers, higher total package sink capacity(200 mA versus 100 mA) that supports having all LEDs on at the same time and moredevice addresses (64 versus 8) are available to allow many more devices on the buswithout address conflicts.
上傳時間： 2013-10-22
上傳用戶：wwwwwen5
The TL2575 and TL2575HV represent superior alternatives to popular three-terminal linear regulators. Due totheir high efficiency, the devices significantly reduce the size of the heatsink and, in many cases, no heatsink isrequired. Optimized for use with standard series of inductors available from several different manufacturers, theTL2575 and TL2575HV greatly simplify the design of switch-mode power supplies by requiring a minimaladdition of only four to six external components for operation.
標簽： STEP-DOWN SWITCHING SIMPLE 1A
上傳時間： 2013-11-20
上傳用戶：jelenecheung
該文介紹了開關磁阻電機的基本原理，設計了一種用80C196 單片機實現的開關磁阻電機驅動系統，并對該開關磁阻電機調速系統的性能進行了實驗與測試，實驗證明該系統運行可靠。開關磁阻電動機是磁阻電動機與電子開關驅動控制器組成的控制裝置，又稱開關磁阻電機驅動系統（Switched Reluctance Motor drive,簡稱SRD）。電機結構簡單堅固，運行可靠，系統具有啟動轉矩高、啟動電流低、調速范圍寬、運行效率高，特別適用于頻繁啟停及正反轉運行，使得SRD 成為交，直流電機驅動系統以及無刷直流電機驅動系統的強有力競爭者。目前，SRD 已用于多個領域，如：電動車驅動、家用電器、伺服與調速系統等許多領域。本文設計了一個以 80C196 單片機為控制核心的SRD 的控制系統，充分利用了SRD 電機控制方式靈活的特點，采用數字化控制系統對SR 電機進行控制，簡化了硬件電路，提高了系統的可靠性。
上傳時間： 2013-11-05
上傳用戶：18711024007
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標簽： synchronous Emulating serial
上傳時間： 2014-01-31
上傳用戶：z1191176801
Presents short and simple I2C software routines that support onlyslave (rather than master or master & slave) operation and an ASMdemonstration program. The slave-only software in this app notecomplements the master mode software presented in AN464, Usingthe 87LPC76X microcontroller as an I2C bus master.
上傳時間： 2013-11-22
上傳用戶：1039312764
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標簽： Spartan-XL Express XAPP FPGA
上傳時間： 2014-12-28
上傳用戶：hewenzhi
為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上傳時間： 2014-01-13
上傳用戶：qoovoop
a8259 可編程中斷控制 altera提供 The a8259 is designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時間： 2014-11-29
上傳用戶：zhyiroy
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上傳時間： 2013-11-01
上傳用戶：truth12
The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/Output (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.
上傳時間： 2013-10-26
上傳用戶：yuzsu
