Nios II 軟件開發(fā)人員手冊(cè)中的緩存和緊耦合存儲(chǔ)器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:
標(biāo)簽： Nios 軟件開發(fā) 存儲(chǔ)器
上傳時(shí)間： 2013-10-25
上傳用戶：蟲蟲蟲蟲蟲蟲
The CoolRunner-II CPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
上傳時(shí)間： 2013-11-03
上傳用戶：1037540470
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上傳時(shí)間： 2013-12-07
上傳用戶：bruce
WP369可擴(kuò)展式處理平臺(tái)-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
標(biāo)簽： 369 WP 擴(kuò)展式 處理平臺(tái)
上傳時(shí)間： 2013-10-18
上傳用戶：cursor
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
標(biāo)簽： FPGA PLD 數(shù)據(jù)加密
上傳時(shí)間： 2013-10-20
上傳用戶：磊子226
針對(duì)嵌入式機(jī)器視覺系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機(jī)。基于對(duì)智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對(duì)國(guó)內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺(tái)，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行，完成圖像獲取與分析，并作出相應(yīng)輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
標(biāo)簽： FPGA DSP 模式 智能相機(jī)
上傳時(shí)間： 2013-11-14
上傳用戶：無聊來刷下
ref-sdr-sdram-vhdl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上傳時(shí)間： 2013-10-23
上傳用戶：半熟1994
ISA總線概述 ISA總線: (Industry Standard architecture:工業(yè)標(biāo)準(zhǔn)體系結(jié)構(gòu)）是IBM公司為PC/AT電腦而制定的總線標(biāo)準(zhǔn)，為16位體系結(jié)構(gòu)，只能支持16位的I/O設(shè)備，數(shù)據(jù)傳輸率大約是16MB/S。也稱為AT標(biāo)準(zhǔn)。開始時(shí)PC機(jī)面向個(gè)人及辦公室，定義了8位的ISA總線結(jié)構(gòu)，對(duì)外公開，成為標(biāo)準(zhǔn)（ISO ISA標(biāo)準(zhǔn)）。第三方開發(fā)出許多ISA擴(kuò)充板卡，推動(dòng)了PC機(jī)的發(fā)展。1984年推出IBM-PC/AT系統(tǒng)，ISA從8位擴(kuò)充到16位，地址線從20條擴(kuò)充到24條。1988年，康柏、HP、NEC等9個(gè)廠商協(xié)同把ISA擴(kuò)展到32位，即EISA總線(Extended ISA)。
標(biāo)簽： ISA 104 PC 總線規(guī)范
上傳時(shí)間： 2013-10-16
上傳用戶：dajin
XMDS is a code generator that integrates equations. You write them down in human readable form in a XML file, and it goes away and writes and compiles a C++ program that integrates those equations as fast as it can possibly be done in your architecture.
標(biāo)簽： integrates generator equations readable
上傳時(shí)間： 2014-11-27
上傳用戶：hebmuljb
ava加密擴(kuò)展即Java Cryptography Extension，簡(jiǎn)稱JCE。它是Sun的加密服務(wù)軟件，包含了加密和密匙生成功能。JCE是JCA（Java Cryptography architecture）的一種擴(kuò)展。 JCE沒有規(guī)定具體的加密算法，但提供了一個(gè)框架，加密算法的具體實(shí)現(xiàn)可以作為服務(wù)提供者加入。除了JCE框架之外，JCE軟件包還包含了SunJCE服務(wù)提供者，其中包括許多有用的加密算法，比如DES（Data Encryption Standard）和Blowfish。 為簡(jiǎn)單計(jì)，在本文中我們將用DES算法加密和解密字節(jié)碼。下面是用JCE加密和解密數(shù)據(jù)必須遵循的基本步驟： 步驟1：生成一個(gè)安全密匙。在加密或解密任何數(shù)據(jù)之前需要有一個(gè)密匙。密匙是隨同被加密的應(yīng)用一起發(fā)布的一小段數(shù)據(jù)，Listing 3顯示了如何生成一個(gè)密匙。 【Listing 3：生成一個(gè)密匙】
標(biāo)簽： Cryptography Extension Java ava
上傳時(shí)間： 2015-03-26
上傳用戶：nanxia
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