-
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
標(biāo)簽：
Bridge
Memory
Contr
MPC
上傳時間：
2013-10-08
上傳用戶：18711024007
-
The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 MicrocontrollerCore. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementationof the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision1.1.This application note describes a demonstration program that has been written for the DK3200 hardwaredemonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to workwith the device, using the HID class as a ready-made device driver for the USB connection.IN-APPLICATION-PROGRAMMING (IAP) AND IN-SYSTEM-PROGRAMMING (ISP)Since the μPSD contains two independent Flash memory arrays, the Micro Controller Unit (MCU) can executecode from one memory while erasing and programming the other. Product firmware updates in thefield can be reliably performed over any communication channel (such as CAN, Ethernet, UART, J1850)using this unique architecture. For In-Application-Programming (IAP), all code is updated through theMCU. The main advantage for the user is that the firmware can be updated remotely. The target applicationruns and takes care on its own program code and data memory.IAP is not the only method to program the firmware in μPSD devices. They can also be programmed usingIn-System-Programming (ISP). A IEEE1149.1-compliant JTAG interface is included on the μPSD. Withthis, the entire device can be rapidly programmed while soldered to the circuit board (Main Flash memory,Secondary Boot Flash memory, the PLD, and all configuration areas). This requires no MCU participation.The MCU is completely bypassed. So, the μPSD can be programmed or reprogrammed any time, anywhere, even when completely uncommitted.Both methods take place with the device in its normal hardware environment, soldered to a printed circuitboard. The IAP method cannot be used without previous use of ISP, because IAP utilizes a small amountof resident code to receive the service commands, and to perform the desired operations.
標(biāo)簽：
Demonstration
3200
USB
for
上傳時間：
2014-02-27
上傳用戶：zhangzhenyu
-
The XA-S3 is a member of Philips Semiconductors’ XA (eXtended architecture) family of high performance 16-bit single-chip Microcontrollers. The XA-S3 combines many powerful peripherals on one chip. Therefore, it is suited for general multipurpose high performance embedded control functions.One of the on-chip peripherals is the I2C bus interface. This report describes worked-out driver software (written in C) to program / use the I2C interface of the XA-S3. The driver software, together with a demo program and interface software routines offer the user a quick start in writing a complete I2C - XAS3 system application.
標(biāo)簽：
XA-S
IIC
C語言
接口
上傳時間：
2013-11-10
上傳用戶：liaofamous
-
計算機(jī)部件要具有通用性，適應(yīng)不同系統(tǒng)與不同用戶的需求，設(shè)計必須模塊化。計算機(jī)部件產(chǎn)品(模塊)供應(yīng)出現(xiàn)多元化。模塊之間的聯(lián)接關(guān)系要標(biāo)準(zhǔn)化，使模塊具有通用性。模塊設(shè)計必須基于一種大多數(shù)廠商認(rèn)可的模塊聯(lián)接關(guān)系，即一種總線標(biāo)準(zhǔn)。總線的標(biāo)準(zhǔn)總線是一類信號線的集合是模塊間傳輸信息的公共通道，通過它，計算機(jī)各部件間可進(jìn)行各種數(shù)據(jù)和命令的傳送。為使不同供應(yīng)商的產(chǎn)品間能夠互換，給用戶更多的選擇，總線的技術(shù)規(guī)范要標(biāo)準(zhǔn)化。總線的標(biāo)準(zhǔn)制定要經(jīng)周密考慮，要有嚴(yán)格的規(guī)定。總線標(biāo)準(zhǔn)（技術(shù)規(guī)范）包括以下幾部分：機(jī)械結(jié)構(gòu)規(guī)范：模塊尺寸、總線插頭、總線接插件以及按裝尺寸均有統(tǒng)一規(guī)定。功能規(guī)范：總線每條信號線（引腳的名稱）、功能以及工作過程要有統(tǒng)一規(guī)定。電氣規(guī)范：總線每條信號線的有效電平、動態(tài)轉(zhuǎn)換時間、負(fù)載能力等。總線的發(fā)展情況S-100總線：產(chǎn)生于1975年，第一個標(biāo)準(zhǔn)化總線，為微計算機(jī)技術(shù)發(fā)展起到了推動作用。IBM-PC個人計算機(jī)采用總線結(jié)構(gòu)（Industry Standard architecture, ISA)并成為工業(yè)化的標(biāo)準(zhǔn)。先后出現(xiàn)8位ISA總線、16位ISA總線以及后來兼容廠商推出的EISA（Extended ISA)32位ISA總線。為了適應(yīng)微處理器性能的提高及I/O模塊更高吞吐率的要求，出現(xiàn)了VL-Bus(VESA Local Bus)和PCI(Peripheral Component Interconnect,PCI）總線。適合小型化要求的PCMCIA(Personal Computer Memory Card International Association)總線，用于筆記本計算機(jī)的功能擴(kuò)展。總線的指標(biāo)計算機(jī)主機(jī)性能迅速提高,各功能模塊性能也要相應(yīng)提高,這對總線性能提出更高的要求。總線主要技術(shù)指標(biāo)有幾方面：總線寬度：一次操作可以傳輸?shù)臄?shù)據(jù)位數(shù)，如S100為8位，ISA為16位，EISA為32位，PCI-2可達(dá)64位。總線寬度不會超過微處理器外部數(shù)據(jù)總線的寬度。總數(shù)工作頻率：總線信號中有一個CLK時鐘，CLK越高每秒鐘傳輸?shù)臄?shù)據(jù)量越大。ISA、EISA為8MHz，PCI為33.3MHz, PCI-2可達(dá)達(dá)66.6MHz。單個數(shù)據(jù)傳輸周期：不同的傳輸方式，每個數(shù)據(jù)傳輸所用CLK周期數(shù)不同。ISA要2個，PCI用1個CLK周期。這決定總線最高數(shù)據(jù)傳輸率。5. 總線的分類與層次系統(tǒng)總線：是微處理器芯片對外引線信號的延伸或映射，是微處理器與片外存儲器及I/0接口傳輸信息的通路。系統(tǒng)總線信號按功能可分為三類：地址總線（Where）：指出數(shù)據(jù)的來源與去向。地址總線的位數(shù)決定了存儲空間的大小。系統(tǒng)總線：數(shù)據(jù)總線（What）提供模塊間傳輸數(shù)據(jù)的路徑，數(shù)據(jù)總線的位數(shù)決定微處理器結(jié)構(gòu)的復(fù)雜度及總體性能。控制總線（When）：提供系統(tǒng)操作所必需的控制信號，對操作過程進(jìn)行控制與定時。擴(kuò)充總線：亦稱設(shè)備總線，用于系統(tǒng)I/O擴(kuò)充。與系統(tǒng)總線工作頻率不同，經(jīng)接口電路對系統(tǒng)總統(tǒng)信號緩沖、變換、隔離，進(jìn)行不同層次的操作（ISA、EISA、MCA)局部總線：擴(kuò)充總線不能滿足高性能設(shè)備（圖形、視頻、網(wǎng)絡(luò)）接口的要求，在系統(tǒng)總線與擴(kuò)充總線之間插入一層總線。由于它經(jīng)橋接器與系統(tǒng)總線直接相連，因此稱之為局部總線（PCI）。
標(biāo)簽：
微型計算機(jī)
總線
上傳時間：
2013-11-09
上傳用戶：nshark
-
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation architecture for Your Next-Generation architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時間：
2013-11-13
上傳用戶：瓦力瓦力hong
-
Xilinx Next Generation 28 nm FPGA Technology Overview
Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
標(biāo)簽：
Xilinx
FPGA
312
WP
上傳時間：
2014-12-28
上傳用戶：zhang97080564
-
WP369可擴(kuò)展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
標(biāo)簽：
369
WP
擴(kuò)展式
處理平臺
上傳時間：
2013-10-22
上傳用戶：685
-
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
標(biāo)簽：
FPGA
PLD
數(shù)據(jù)加密
上傳時間：
2013-11-06
上傳用戶：wl9454
-
針對嵌入式機(jī)器視覺系統(tǒng)向獨立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機(jī)。基于對智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對國內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計可以實現(xiàn)脫離PC運行，完成圖像獲取與分析，并作出相應(yīng)輸出。
Abstract:
This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
標(biāo)簽：
FPGA
DSP
模式
智能相機(jī)
上傳時間：
2013-10-24
上傳用戶：bvdragon
-
ref-sdr-sdram-vhdl代碼
SDR SDRAM Controller v1.1 readme.txt
This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.
The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture.
Last updated September, 2002
Copyright ?2002 Altera Corporation. All rights reserved.
標(biāo)簽：
sdram
vhdl
ref
sdr
上傳時間：
2013-11-13
上傳用戶：takako_yang
