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functional

LPC1700系列芯片勘誤手冊

This errata sheet describes both the known functional problems and anydeviations from the electrical specifications known at the release date ofthis document.Each deviation is assigned a number and its history is tracked in a table atthe end of the document.

標簽： 1700 LPC 系列芯片勘誤

上傳時間： 2013-11-22

上傳用戶：liangliang123
LPC1100系列微控制器勘誤手冊

This errata sheet describes both the known functional problems and anydeviations from the electrical specifications known at the release date ofthis document.Each deviation is assigned a number and its history is tracked in a table atthe end of the document.

標簽： 1100 LPC 微控制器勘誤

上傳時間： 2014-12-31

上傳用戶：thuyenvinh
如何仿真IP核(建立modelsim仿真庫完整解析)

　　IP核生成文件：（Xilinx/Altera 同）　　IP核生成器生成 ip 后有兩個文件對我們比較有用，假設生成了一個 asyn_fifo 的核，則asyn_fifo.veo 給出了例化該核方式（或者在 Edit－》Language Template-》COREGEN 中找到verilog/VHDL 的例化方式）。asyn_fifo.v 是該核的行為模型，主要調用了 xilinx 行為模型庫的模塊，仿真時該文件也要加入工程。（在 ISE中點中該核，在對應的 processes 窗口中運行“ View Verilog functional Model ”即可查看該 .v 文件）。如下圖所示。

標簽： modelsim 仿真 IP核仿真庫

上傳時間： 2013-10-20

上傳用戶：lingfei
AXI總線功能模塊v1.1產品簡介（英文資料）

AXI Bus functional Model v1.1 Product Brief.pdf

標簽： AXI 1.1 總線產品簡介

上傳時間： 2015-01-01

上傳用戶：kbnswdifs
采用TüV認證的FPGA開發功能安全系統

This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System

標簽： FPGA 安全系統

上傳時間： 2013-11-14

上傳用戶：zoudejile
《器件封裝用戶向導》賽靈思產品封裝資料

Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.

標簽： 封裝器件用戶賽靈思

上傳時間： 2013-11-21

上傳用戶：不懂夜的黑
WP151 - Xilinx FPGA的System ACE配置解決方案

Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bolstered both the design challenges and theopportunities to develop modern electronic systems.One trend driving these changes is the increasedintegration of core logic with previously discretefunctions to achieve higher performance and morecompact board designs.

標簽： System Xilinx FPGA 151

上傳時間： 2013-11-23

上傳用戶：kangqiaoyibie
XAPP380 -利用CoolRunner-II CPLD創建交叉點開關

This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.

標簽： CoolRunner-II XAPP CPLD 380

上傳時間： 2013-10-26

上傳用戶：kiklkook
SOC驗證方法

Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.

標簽： SOC 驗證方法

上傳時間： 2013-11-19

上傳用戶：m62383408
如何仿真IP核(建立modelsim仿真庫完整解析)

　　IP核生成文件：（Xilinx/Altera 同）　　IP核生成器生成 ip 后有兩個文件對我們比較有用，假設生成了一個 asyn_fifo 的核，則asyn_fifo.veo 給出了例化該核方式（或者在 Edit－》Language Template-》COREGEN 中找到verilog/VHDL 的例化方式）。asyn_fifo.v 是該核的行為模型，主要調用了 xilinx 行為模型庫的模塊，仿真時該文件也要加入工程。（在 ISE中點中該核，在對應的 processes 窗口中運行“ View Verilog functional Model ”即可查看該 .v 文件）。如下圖所示。

標簽： modelsim 仿真 IP核仿真庫

上傳時間： 2013-11-02

上傳用戶：誰偷了我的麥兜