Linear Technology offers some of the highest performance RF and signal chain solutions for wireless and cellularinfrastructure. These products support worldwide standards including, LTE, WiMAX, GSM,W-CDMA, TD-SCDMA,CDMA, and CDMA2000. Other wireless systems include broadband microwave data links, secure communications,satellite receivers, broadband wireless access, wireless broadcast systems, RFID readers and cable infrastructure
上傳時(shí)間： 2013-11-04
上傳用戶：kiklkook
提出了一種基于PIC16F877A微控制器和CC2500射頻收發(fā)器芯片的低功耗、低成本RFID（Radio Frequency Identification， 無線射頻識(shí)別）局域定位系統(tǒng)設(shè)計(jì)方法，介紹了系統(tǒng)的定位工作原理、主要硬件電路模塊及定位算法的設(shè)計(jì)和實(shí)現(xiàn)。采用基于序列號(hào)對(duì)時(shí)隙數(shù)運(yùn)算的排序算法有效解決了多標(biāo)簽識(shí)別碰撞的問題，基于射頻輻射強(qiáng)度（Received Signal Strength Indication， RSSI）和圓周定位算法實(shí)現(xiàn)了基于RFID多標(biāo)簽系統(tǒng)的平面定位。實(shí)驗(yàn)測(cè)試表明，這種射頻定位方法能夠?qū)崿F(xiàn)一定精度下的無線局域定位的功能。
上傳時(shí)間： 2013-11-06
上傳用戶：weareno2
為解決現(xiàn)Z-Stack定位程序代碼量大，結(jié)構(gòu)復(fù)雜等問題，提出一種基于TinyOS的CC2430定位方案。在分析TinyOS組件架構(gòu)基礎(chǔ)上，設(shè)計(jì)實(shí)現(xiàn)盲節(jié)點(diǎn)、錨節(jié)點(diǎn)與匯聚節(jié)點(diǎn)間的無線通信以及匯聚節(jié)點(diǎn)與PC機(jī)的串口通信。在此基礎(chǔ)上實(shí)現(xiàn)PC對(duì)各錨節(jié)點(diǎn)RSSI（Received Signal Strength Indicator）寄存器值的正確讀取，確定實(shí)驗(yàn)室環(huán)境下對(duì)數(shù)-常態(tài)無線傳播模型的具體參數(shù)，并采用質(zhì)心算法來提高定位精度。實(shí)驗(yàn)顯示，在由四個(gè)錨節(jié)點(diǎn)組成的4.8×3.6 m2矩形定位區(qū)域中，通過RSSI質(zhì)心定位算法求得的盲節(jié)點(diǎn)坐標(biāo)為（2.483 1，1.018 5），實(shí)際坐標(biāo)為（2.40，1.20），誤差為0.199 6 m，表明較好地實(shí)現(xiàn)對(duì)盲節(jié)點(diǎn)的定位。
上傳時(shí)間： 2013-10-21
上傳用戶：whymatalab2
針對(duì)UHF讀寫器設(shè)計(jì)中，在符合EPC Gen2標(biāo)準(zhǔn)的情況下，對(duì)標(biāo)簽返回的高速數(shù)據(jù)進(jìn)行正確解碼以達(dá)到正確讀取標(biāo)簽的要求，提出了一種新的在ARM平臺(tái)下采用邊沿捕獲統(tǒng)計(jì)定時(shí)器數(shù)判斷數(shù)據(jù)的方法，并對(duì)FM0編碼進(jìn)行解碼。與傳統(tǒng)的使用定時(shí)器定時(shí)采樣高低電平的FM0解碼方法相比，該解碼方法可以減少定時(shí)器定時(shí)誤差累積的影響；可以將捕獲定時(shí)器數(shù)中斷與數(shù)據(jù)判斷解碼相對(duì)分隔開，使得中斷對(duì)解碼影響很小，實(shí)現(xiàn)捕獲與解碼的同步。通過實(shí)驗(yàn)表明，這種方法提高了解碼的效率，在160 Kb/s的接收速度下，讀取一張標(biāo)簽的時(shí)間約為30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding， so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.
標(biāo)簽： UHF FM0 讀寫器 解碼技術(shù)
上傳時(shí)間： 2013-11-10
上傳用戶：liufei
Single-Ended and Differential S-Parameters Differential circuits have been important incommunication systems for many years. In the past,differential communication circuits operated at lowfrequencies, where they could be designed andanalyzed using lumped-element models andtechniques. With the frequency of operationincreasing beyond 1GHz, and above 1Gbps fordigital communications, this lumped-elementapproach is no longer valid, because the physicalsize of the circuit approaches the size of awavelength.Distributed models and analysis techniques are nowused instead of lumped-element techniques.Scattering parameters, or S-parameters, have beendeveloped for this purpose [1]. These S-parametersare defined for single-ended networks. S-parameterscan be used to describe differential networks, but astrict definition was not developed until Bockelmanand others addressed this issue [2]. Bockelman’swork also included a study on how to adapt single-ended S-parameters for use with differential circuits[2]. This adaptation, called “mixed-mode S-parameters,” addresses differential and common-mode operation, as well as the conversion betweenthe two modes of operation.This application note will explain the use of single-ended and mixed-mode S-parameters, and the basicconcepts of microwave measurement calibration.
上傳時(shí)間： 2014-03-25
上傳用戶：yyyyyyyyyy
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時(shí)間： 2013-10-28
上傳用戶：15501536189
摘要：介紹了基于數(shù)字信號(hào)處理(Digital Signal Processor,DSP)的運(yùn)動(dòng)控制器GT-800在貼片機(jī)控制系統(tǒng)中的應(yīng)用。該系統(tǒng)采用以PC機(jī)為上位機(jī)、GT-800運(yùn)動(dòng)控制器為下位機(jī)的硬件結(jié)構(gòu)，上下位機(jī)之間的通訊采用基于ISA總線的雙端口RAM的模式，系統(tǒng)的軟件設(shè)計(jì)采用基于VisualC++6．0的軟件設(shè)計(jì)模式。關(guān)鍵詞：GT-800運(yùn)動(dòng)控制器；貼片機(jī)；運(yùn)動(dòng)控制；機(jī)器視覺
標(biāo)簽： 800 GT 貼片機(jī) 控制系統(tǒng)
上傳時(shí)間： 2013-10-18
上傳用戶：asdkin
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時(shí)間： 2013-10-12
上傳用戶：kang1923
以Altera公司的Quartus Ⅱ 7.2作為開發(fā)工具，研究了基于FPGA的DDS IP核設(shè)計(jì)，并給出基于Signal Tap II嵌入式邏輯分析儀的仿真測(cè)試結(jié)果。將設(shè)計(jì)的DDS IP核封裝成為SOPC Builder自定義的組件，結(jié)合32位嵌入式CPU軟核Nios II，構(gòu)成可編程片上系統(tǒng)（SOPC），利用極少的硬件資源實(shí)現(xiàn)了可重構(gòu)信號(hào)源。該系統(tǒng)基本功能都在FPGA芯片內(nèi)完成，利用 SOPC技術(shù)，在一片 FPGA 芯片上實(shí)現(xiàn)了整個(gè)信號(hào)源的硬件開發(fā)平臺(tái)，達(dá)到既簡(jiǎn)化電路設(shè)計(jì)、又提高系統(tǒng)穩(wěn)定性和可靠性的目的。
標(biāo)簽： FPGA DDS IP核 設(shè)計(jì)方案
上傳時(shí)間： 2013-12-22
上傳用戶：forzalife
歡迎使用 PowerPCB 教程。本教程描述了 PADS-PowerPCB 的絕大部分功能和特點(diǎn)，以及使用的各個(gè)過程，這些功能包括： · 基本操作 · 建立元件(Component) · 建立板子邊框線(Board outline) · 輸入網(wǎng)表(Netlist) · 設(shè)置設(shè)計(jì)規(guī)則(Design Rule) · 元件(Part)的布局(Placement) · 手工和交互的布線 · SPECCTRA全自動(dòng)布線器(Route Engine) · 覆銅(Copper Pour) · 建立分隔/混合平面層(Split/mixed Plane) · Microsoft的目標(biāo)連接與嵌入(OLE)(Object Linking Embedding) · 可選擇的裝配選件(Assembly options) · 設(shè)計(jì)規(guī)則檢查(Design Rule Check) · 反向標(biāo)注(Back Annotation) · 繪圖輸出(Plot Output) 使用本教程后，你可以學(xué)到印制電路板設(shè)計(jì)和制造的許多基本知識(shí)。
上傳時(shí)間： 2013-10-08
上傳用戶：x18010875091
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