提出了一個由AT89C52單片機控制步進電機的實例。可以通過鍵盤輸入相關數據, 并根據需要, 實時對步進電機工作方式進行設置, 具有實時性和交互性的特點。該系統可應用于步進電機控制的大多數場合。實踐表明, 系統性能優于傳統的步進電機控制器。關鍵詞: 單片機; 步進電動機; 直流固態繼電器; 實時控制Con trol System of Stepp ingMotor Ba sed on AT89C52 ChipM icrocomputerMENGWu2sheng, L ILiang (College of Automatization, Northwestern Polytechnical Unversity, Xipan 710072, China)ABSTRACT: A stepp ing motor control system based on AT89C52 chip microcomputer was described.The data can be inputwith keyboard, and stepp ingmotorwas controlled by these data. According to the demand, users can set the workingmodel of stepp ingmotor in real2time. This system can be widely used in stepp ing motor controlling. The p ractice showed that the performance of this system outdid the tradi tional stepp ing motor controller.KEY WORDS: Chip microcomputer; Stepp ingmotor; DCSSR; Real2time control
標簽： Control System ingMot Stepp
上傳時間： 2013-11-19
上傳用戶：leesuper
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.
上傳時間： 2013-11-10
上傳用戶：1427796291
針對使用硬件描述語言進行設計存在的問題，提出一種基于FPGA并采用DSP Builder作為設計工具的數字信號處理器設計方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設計流程，設計了一個12階FIR 低通數字濾波器，通過Quartus 時序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測試對設計進行了驗證。結果表明，所設計的FIR 濾波器功能正確，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
上傳時間： 2013-11-17
上傳用戶：lo25643
在綜合分析諧波勵磁無刷同步發電機勵磁控制系統的基礎上,對其勵磁控制策略進行了研究,開發了一套基于DSP( TMS320F2812) 控制的新型柴油發電機勵磁控制系統,該系統采用參數自適應模糊PID 控制勵磁,選用交流采樣方式實時檢測各信號的瞬時特性,系統仿真結果以及在1 臺25 kW 工頻柴油發電機上的試驗結果證明了該控制器具有較好的電壓調節特性,系統穩態和暫態性能完全滿足發電機對勵磁系統的要求。關鍵詞:勵磁調節;模糊PID 控制;數字信號處理器;交流采樣 Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous generator and it s characteristics ,a new type of diesel generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling
上傳時間： 2013-10-29
上傳用戶：fxf126@126.com
設計一種應用于某全地形ATV車載武器裝置中的中控系統，該系統設計是以TMS320F2812型DSP為核心，采用模塊化設計思想，對其硬件部分進行系統設計，能夠完成對武器裝置高低、回轉方向的運動控制，實現靜止或行進狀態中對目標物的測距，自動瞄準以及按既定發射模式發射彈丸和各項安全性能檢測等功能。通過編制相應的軟件，對其進行系統調試，驗證了該設計運行穩定。 Abstract: A central control system applied to an ATV vehicle weapons is designed. The system design is based on TMS320F2812 DSP as the core， uses modular design for its hardware parts. The central control system can complete the motion control of the level of weapons and equipment， rotation direction， to achieve a state of static or moving objects on the target ranging， auto-targeting and according to the established target and the projectile and the launch of the security performance testing and other functions. Through the development of appropriate software and to carry out system testing to verify the stability of this design and operation.
上傳時間： 2013-11-02
上傳用戶：jshailingzzh
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時間： 2013-10-22
上傳用戶：ztj182002
This application note describes how to implement the Bus LVDS (BLVDS) interface in the supported Altera ® device families for high-performance multipoint applications. This application note also shows the performance analysis of a multipoint application with the Cyclone III BLVDS example.
標簽： Implementing LVDS 522 Bus
上傳時間： 2013-11-10
上傳用戶：frank1234
Design techniques for electronic systems areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bolstered both the design challenges and theopportunities to develop modern electronic systems.One trend driving these changes is the increasedintegration of core logic with previously discretefunctions to achieve higher performance and morecompact board designs.
上傳時間： 2014-12-28
上傳用戶：康郎
Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
上傳時間： 2014-12-28
上傳用戶：zhang97080564
