On the LPC13xx, programming, erasure and re-programming of the on-chip flash can be performed using In-System Programming (ISP) via the UART serial port, and also, can be performed using In-Application Programming (IAP) calls directed by the end-user code. For In-System Programming (ISP) via the UART serial port, the ISP command handler (resides in the bootloader) allows erasure of one or more sector (s) of the on-chip flash memory.
標(biāo)簽： 1300 LPC 勘誤 數(shù)據(jù)手冊
上傳時間： 2013-12-13
上傳用戶：lmq0059
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
標(biāo)簽： Modelling Guide Navy VHDL
上傳時間： 2013-11-20
上傳用戶：pzw421125
本文利用Verilog HDL 語言自頂向下的設(shè)計方法設(shè)計多功能數(shù)字鐘，突出了其作為硬件描述語言的良好的可讀性、可移植性和易理解等優(yōu)點，并通過Altera QuartusⅡ 4.1 和ModelSim SE 6.0 完成綜合、仿真。此程序通過下載到FPGA 芯片后，可應(yīng)用于實際的數(shù)字鐘顯示中。 關(guān)鍵詞：Verilog HDL；硬件描述語言；FPGA Abstract: In this paper, the process of designing multifunctional digital clock by the Verilog HDL top-down design method is presented, which has shown the readability, portability and easily understanding of Verilog HDL as a hard description language. Circuit synthesis and simulation are performed by Altera QuartusⅡ 4.1 and ModelSim SE 6.0. The program can be used in the truly digital clock display by downloading to the FPGA chip. Keywords: Verilog HDL；hardware description language；FPGA
標(biāo)簽： Verilog HDL 多功能 數(shù)字
上傳時間： 2013-11-10
上傳用戶：hz07104032
Abstract: Many modern industrial, medical, and commercial applications require temperature measurements in the extended temperature rangewith accuracies of ±0.3°C or better, performed with reasonable cost and often with low power consumption. This article explains how platinumresistance temperature detectors (PRTDs) can perform measurements over wide temperature ranges of -200°C to +850°C, with absolute accuracyand repeatability better than ±0.3°C, when used with modern processors capable of resolving nonlinear mathematical equation quickly and costeffectively. This article is the second installment of a series on PRTDs. For the first installment, please read application note 4875, "High-Accuracy Temperature Measurements Call for Platinum Resistance Temperature Detectors (PRTDs) and Precision Delta-Sigma ADCs."
上傳時間： 2013-11-06
上傳用戶：WMC_geophy
This applet illustrates the prediction capabilities of the multi-layer perceptrons. It allows to define an input signal on which prediction will be performed. The user can choose the number of input units, hidden units and output units, as well as the delay between the input series and the predicted output series. Then it is possible to observe interesting prediction properties.
標(biāo)簽： capabilities illustrates multi-layer perceptrons
上傳時間： 2015-06-17
上傳用戶：lnnn30
This PNG Delphi version 1.56 documentation (this version is a major rewrite intended to replace the previous version, 1.2). Improvements in this new version includes: This new version allows the programmer to not use Delphi heavy units which will greatly reduce the size of the final executable. Read more about this feature here. Most, if not all, Portable Network Graphics features as CRC checking are now fully performed. Error on broken images are now better handled using new exception classes. The images may be saved using interlaced mode also. Transparency information won t be discarted after the image is loaded any more. Most of the images are decoded much faster now. The images will be better encoded using fresh new algorithms. IMPORTANT! Now transparency information is used to display images.
標(biāo)簽： version documentation intended rewrite
上傳時間： 2015-06-28
上傳用戶：qiao8960
Simulation of RM(1,3), equivalent to the (8,4,4) extended Hamming code. Soft-decision decoding performed by the Green machine
標(biāo)簽： Soft-decision Simulation equivalent decoding
上傳時間： 2015-07-05
上傳用戶：lindor
關(guān)于FPGA流水線設(shè)計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
C-Talk is interpreted scripting language with C-like syntax and dynamic type checking. Variables in C-Talk have no type. So there is no compile time type checking in C-Talk, all checking is performed at runtime. To preserve reference integrity, explicit memory deallocation is prohibited in C-Talk, unused objects are automatically deallocated by garbage collector.
標(biāo)簽： interpreted Variables scripting checking
上傳時間： 2015-08-18
上傳用戶：王者A
This code was used for making the practical measurements in section 2.3 of my thesis. This Matlab code allows an OFDM signal to be generated based on an input data file. The data can be random data, a grey scale image, a wave file, or any type of file. The generated OFDM signal is stored as a windows wave file, allowing it to be viewed, listened to and manipulated in other programs. The modified wave file can then be decoded by the receiver software to extract the original data. This code was developed for the experiments that I performed in my honours thesis, and thus has not been fully debugged. This is the original code developed for the thesis and so has several problems with it. The BER performance given by the simulations is infact Symbol Error Rate.
標(biāo)簽： This measurements practical section
上傳時間： 2015-09-20
上傳用戶：tedo811
蟲蟲下載站版權(quán)所有 京ICP備2021023401號-1
