Abstract: Communication with 1-Wire slave devices requires a 1-Wire master. There are numerous ways to build a 1-Wire master (see reference design 4206, "Choosing the Right 1-Wire Master for Embedded Applications"). Thisdocument describes the DS1WM, a synthesizable 1-Wire master that can be implemented in an application-specificintegrated circuit (ASIC) or field-programmable gate array (FPGA).
IDCT-M is a medium speed 1D IDCT core
-- it can accept a continous stream of 12-bit input words at a rate of
-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP@ML MPEG video
-- the core is 100％ synthesizable
一個(gè)簡(jiǎn)單的ＳＰＩ ＩＰ核，SPI Core Specifications 可以從說(shuō)明文檔中找到！
The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires.
FEATURES:
· Compatible with Motorola’s SPI specifications
· Enhanced M68HC11 Serial Peripheral Interface
· 4 entries deep read FIFO
· 4 entries deep write FIFO
· Interrupt generation after 1, 2, 3, or 4 transferred bytes
· 8 bit WISHBONE RevB.3 Classic interface
· Operates from a wide range of input clock frequencies
· Static synchronous design
· Fully synthesizable
This lab exercise will introduce you to the AccelWare IP generators. AccelWare is a library of over fifty IP generators, available in the form of three toolkits that produce synthesizable MATLAB for common MATLAB built in and toolbox functions. Each generator offers macro and micro-architecture selections that allow full customization of the generated model to the target application requirements.
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計(jì)文檔。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.
