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system-<b>On</b>-chip

  • C8051F020數(shù)據(jù)手冊

      The C8051F020/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins (C8051F020/2) or 32 digital I/O pins (C8051F021/3). Highlighted features are listed below; refer to Table 1.1 for specific product feature selection.

    標簽: C8051F020 數(shù)據(jù)手冊

    上傳時間: 2013-11-08

    上傳用戶:lwq11

  • 接口選擇指南

    LVDS、xECL、CML(低電壓差分信號傳輸、發(fā)射級耦合邏輯、電流模式邏輯)………4多點式低電壓差分信號傳輸(M-LVDS) ……………………………………………………8數(shù)字隔離器 ………………………………………………………………………………10RS-485/422 …………………………………………………………………………………11RS-232………………………………………………………………………………………13UART(通用異步收發(fā)機)…………………………………………………………………16CAN(控制器局域網(wǎng))……………………………………………………………………18FlatLinkTM 3G ………………………………………………………………………………19SerDes(串行G 比特收發(fā)機及LVDS)……………………………………………………20DVI(數(shù)字視頻接口)/PanelBusTM ………………………………………………………22TMDS(最小化傳輸差分信號) …………………………………………………………24USB 集線器控制器及外設(shè)器件 …………………………………………………………25USB 接口保護 ……………………………………………………………………………26USB 電源管理 ……………………………………………………………………………27PCI Express® ………………………………………………………………………………29PCI 橋接器 …………………………………………………………………………………33卡總線 (CardBus) 電源開關(guān) ………………………………………………………………341394 (FireWire®, 火線®) ……………………………………………………………………36GTLP (Gunning Transceiver Logic Plus,體效應(yīng)收發(fā)機邏輯+) ………………………………39VME(Versa Module Eurocard)總線 ………………………………………………………41時鐘分配電路 ……………………………………………………………………………42交叉參考指南 ……………………………………………………………………………43器件索引 …………………………………………………………………………………47技術(shù)支持 …………………………………………………………………………………48 德州儀器(TI)為您提供了完備的接口解決方案,使得您的產(chǎn)品別具一格,并加速了產(chǎn)品面市。憑借著在高速、復(fù)合信號電路、系統(tǒng)級芯片 (system-on-a-chip ) 集成以及先進的產(chǎn)品開發(fā)工藝方面的技術(shù)專長,我們將能為您提供硅芯片、支持工具、軟件和技術(shù)文檔,使您能夠按時的完成并將最佳的產(chǎn)品推向市場,同時占據(jù)一個具有競爭力的價格。本選擇指南為您提供與下列器件系列有關(guān)的設(shè)計考慮因素、技術(shù)概述、產(chǎn)品組合圖示、參數(shù)表以及資源信息:

    標簽: 接口 選擇指南

    上傳時間: 2013-10-21

    上傳用戶:Jerry_Chow

  • 《器件封裝用戶向?qū)А焚愳`思產(chǎn)品封裝資料

    Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.

    標簽: 封裝 器件 用戶 賽靈思

    上傳時間: 2013-11-21

    上傳用戶:不懂夜的黑

  • 數(shù)字運算

    數(shù)字運算,判斷一個數(shù)是否接近素數(shù) A Niven number is a number such that the sum of its digits divides itself. For example, 111 is a Niven number because the sum of its digits is 3, which divides 111. We can also specify a number in another base b, and a number in base b is a Niven number if the sum of its digits divides its value. Given b (2 <= b <= 10) and a number in base b, determine whether it is a Niven number or not. Input Each line of input contains the base b, followed by a string of digits representing a positive integer in that base. There are no leading zeroes. The input is terminated by a line consisting of 0 alone. Output For each case, print "yes" on a line if the given number is a Niven number, and "no" otherwise. Sample Input 10 111 2 110 10 123 6 1000 8 2314 0 Sample Output yes yes no yes no

    標簽: 數(shù)字 運算

    上傳時間: 2015-05-21

    上傳用戶:daguda

  • A book describle in detail about the system security and usability technology. It is a system book o

    A book describle in detail about the system security and usability technology. It is a system book on security.

    標簽: system book technology describle

    上傳時間: 2015-07-22

    上傳用戶:zmy123

  • The cable compensation system is an experiment system that performs simulations of partial or microg

    The cable compensation system is an experiment system that performs simulations of partial or microgravity environments on earth. It is a highly nonlinear and complex system.In this paper, a network based on the theory of the Fuzzy Cerebellum Model Articulation Controller(FCMAC) is proposed to control this cable compensation system. In FCMAC ,without appropriate learning rate, the control system based on FCMAC will become unstable or its convergence speed will become slow.In order to guarantee the convergence of tracking error, we present a new kind of optimization based on adaptive GA for selecting learning rate.Furthermore, this approach is evaluated and its performance is discussed.The simulation results shows that performance of the FCMAC based the proposed method is stable and more effective.

    標簽: system compensation simulations experiment

    上傳時間: 2015-08-26

    上傳用戶:希醬大魔王

  • 20世紀90年代中期

    20世紀90年代中期,因使用ASIC實現(xiàn)芯片組受到啟發(fā),萌生應(yīng)該將完整計算機所有不同的功能塊一 次直接集成于一顆硅片上的想法。這種芯片,初始起名叫System on a Chip(SoC),直譯的中文名是 系統(tǒng)級芯片

    標簽:

    上傳時間: 2014-12-20

    上傳用戶:牛布牛

  • We have a group of N items (represented by integers from 1 to N), and we know that there is some tot

    We have a group of N items (represented by integers from 1 to N), and we know that there is some total order defined for these items. You may assume that no two elements will be equal (for all a, b: a<b or b<a). However, it is expensive to compare two items. Your task is to make a number of comparisons, and then output the sorted order. The cost of determining if a < b is given by the bth integer of element a of costs (space delimited), which is the same as the ath integer of element b. Naturally, you will be judged on the total cost of the comparisons you make before outputting the sorted order. If your order is incorrect, you will receive a 0. Otherwise, your score will be opt/cost, where opt is the best cost anyone has achieved and cost is the total cost of the comparisons you make (so your score for a test case will be between 0 and 1). Your score for the problem will simply be the sum of your scores for the individual test cases.

    標簽: represented integers group items

    上傳時間: 2016-01-17

    上傳用戶:jeffery

  • The XML Toolbox converts MATLAB data types (such as double, char, struct, complex, sparse, logical)

    The XML Toolbox converts MATLAB data types (such as double, char, struct, complex, sparse, logical) of any level of nesting to XML format and vice versa. For example, >> project.name = MyProject >> project.id = 1234 >> project.param.a = 3.1415 >> project.param.b = 42 becomes with str=xml_format(project, off ) "<project> <name>MyProject</name> <id>1234</id> <param> <a>3.1415</a> <b>42</b> </param> </project>" On the other hand, if an XML string XStr is given, this can be converted easily to a MATLAB data type or structure V with the command V=xml_parse(XStr).

    標簽: converts Toolbox complex logical

    上傳時間: 2016-02-12

    上傳用戶:a673761058

  • 數(shù)字存儲器和混合信號超大規(guī)模集成電路 本書系統(tǒng)地介紹了數(shù)字、存儲器和混合信號VLSI系統(tǒng)的測試和可測試性設(shè)計。該書是根據(jù)作者多年的科研成果和教學實踐

    數(shù)字存儲器和混合信號超大規(guī)模集成電路 本書系統(tǒng)地介紹了數(shù)字、存儲器和混合信號VLSI系統(tǒng)的測試和可測試性設(shè)計。該書是根據(jù)作者多年的科研成果和教學實踐,結(jié)合國際上關(guān)注的最新研究熱點并參考大量的文獻撰寫的。全書共分三個部分。第一部分是測試基礎(chǔ),介紹了測試基本概念、測試設(shè)備、測試經(jīng)濟學和故障模型。第二部分是測試方法,詳細論述了組合和時序電路的測試生成、存儲器測試、基于DSP和基于模塊的模擬與混合信號測試、延遲測試和IDDQ測試等。第三部分是可測試性設(shè)計,包括掃描設(shè)計、BIST、邊界掃描測試、模擬測試總線標準和基于IP芯核的SOC(System on a chip)測試。

    標簽: VLSI 數(shù)字 存儲器 混合信號

    上傳時間: 2013-11-26

    上傳用戶:hullow

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