VHDL Design of BCD to 7-segment decoder using PROM
資源簡(jiǎn)介：VHDL Design of BCD to 7-segment decoder using PROM
上傳時(shí)間： 2017-07-28
上傳用戶(hù)：Amygdala
資源簡(jiǎn)介：this program will give the functionality of bcd to seven segment display
上傳時(shí)間： 2017-06-02
上傳用戶(hù)：er1219
資源簡(jiǎn)介：CONVERSOR BCD TO 7 segmentS DISPLAY
上傳時(shí)間： 2014-01-16
上傳用戶(hù)：Yukiseop
資源簡(jiǎn)介：英文描述： BCD to 7-segment decoder/Driver with Open-Collector Outputs 中文描述： BCD碼到7段解碼器/驅(qū)動(dòng)器，集電極開(kāi)路輸出
上傳時(shí)間： 2013-07-14
上傳用戶(hù)：m62383408
資源簡(jiǎn)介：this doc willl show you how to control GLCD of nokia6610 to display your imagine using microcontroller
上傳時(shí)間： 2013-12-31
上傳用戶(hù)：windwolf2000
資源簡(jiǎn)介：英文描述： BCD-to-Seven-segment decoder Driver(Internal Pull-up outputs) 中文描述： BCD碼到七段解碼器驅(qū)動(dòng)程序（內(nèi)部上拉輸出）
上傳時(shí)間： 2013-07-13
上傳用戶(hù)：cc1015285075
資源簡(jiǎn)介：a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
上傳時(shí)間： 2014-12-04
上傳用戶(hù)：wkchong
資源簡(jiǎn)介：模擬集成電路的設(shè)計(jì)與其說(shuō)是一門(mén)技術(shù)，還不如說(shuō)是一門(mén)藝術(shù)。它比數(shù)字集成電路設(shè)計(jì)需要更嚴(yán)格的分析和更豐富的直覺(jué)。嚴(yán)謹(jǐn)堅(jiān)實(shí)的理論無(wú)疑是嚴(yán)格分析能力的基石，而設(shè)計(jì)者的實(shí)踐經(jīng)驗(yàn)無(wú)疑是誕生豐富直覺(jué)的源泉。這也正足初學(xué)者對(duì)學(xué)習(xí)模擬集成電路設(shè)計(jì)感到困惑并難...
上傳時(shí)間： 2014-12-23
上傳用戶(hù)：杜瑩12345
資源簡(jiǎn)介：To increase simulation speed, ModelSim® can apply a variety of optimizations to your Design. These include, but are not limited to, mergingprocesses, pulling constants out of loops, clock suppression, and signal collapsing. You control t...
上傳時(shí)間： 2013-12-25
上傳用戶(hù)：pkkkkp
資源簡(jiǎn)介：一本很好的關(guān)于學(xué)習(xí)VHDL的書(shū),Fundamentals of Digital Logic with VHDL Design,我的導(dǎo)師在教我VHDL時(shí)使用的教材.上傳的是書(shū)內(nèi)包含的所有的代碼.
上傳時(shí)間： 2016-01-28
上傳用戶(hù)：戀天使569
資源簡(jiǎn)介：PCI vhdl for Fpga Designer to Design PCI IP
上傳時(shí)間： 2016-03-06
上傳用戶(hù)：lijianyu172
資源簡(jiǎn)介：This paper provides a rigorous comprehensive approach to the Design of the principal software algorithmsutilized inmodern-day strapdown inertial navigationsystems: integration of angular rate into attitude, acceleration transformation/int...
上傳時(shí)間： 2016-10-18
上傳用戶(hù)：蠢蠢66
資源簡(jiǎn)介：2_4 decoder that file contain vhdl code of decoder
上傳時(shí)間： 2013-11-27
上傳用戶(hù)：cooran
資源簡(jiǎn)介：This is 7-segment LED contoler in vhdl
上傳時(shí)間： 2013-12-30
上傳用戶(hù)：123456wh
資源簡(jiǎn)介：This project shows the temperature on a three digit 7-segment display, it measures the temperature from -9.5 to 99 degrees Celcius in 0.5 C steps, or from 0 to 210 degrees Fahrenheit in 1.0 degrees steps. Because of the LED display the temp...
上傳時(shí)間： 2017-04-16
上傳用戶(hù)：xuanjie
資源簡(jiǎn)介：EMC/EMI Design guidelines which would be of help to embedded Designers . The are the basic ideas regarding EMI/EMC
上傳時(shí)間： 2017-05-06
上傳用戶(hù)：xauthu
資源簡(jiǎn)介：Interfacing AVR to LED, Tact switch+7-segment, Matrix Keypad, HD44780 Character LCD and LED dot matrix. Compiler: CodeVisionAVR. Proteus simulation included.
上傳時(shí)間： 2017-09-10
上傳用戶(hù)：dongqiangqiang
資源簡(jiǎn)介：cledlabel component let you add 7 segment edit box to your application. I added floatingpointformat function that let you add float data to the screen
上傳時(shí)間： 2017-09-17
上傳用戶(hù)：許小華
資源簡(jiǎn)介：DSPack is a set of Components and class to write Multimedia Applications using MS Direct Show and DirectX technologies. DSPack is Designed to work with DirectX 9 on Win9X, ME, 2000, and Windows XP operating systems. Now VMR (Video Mixing Re...
上傳時(shí)間： 2015-07-20
上傳用戶(hù)：hanli8870
資源簡(jiǎn)介：Designing the mode mini manual provided the software Design of 23 kinds of typical models mode, the in aid of procedure member was better to develop procedure.
上傳時(shí)間： 2014-01-19
上傳用戶(hù)：bruce5996
資源簡(jiǎn)介：關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL Design of a parameter...
上傳時(shí)間： 2015-07-26
上傳用戶(hù)：CHINA526
資源簡(jiǎn)介：initial working phase of the Design of said editor, featuring multicasting, advanced linux keyboard handling, sub-hierarchical expansion, and multiple cursors (similar to the concept found in moonedit). The author respectfully requests y...
上傳時(shí)間： 2015-08-27
上傳用戶(hù)：invtnewer
資源簡(jiǎn)介：This leon3 Design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. ...
上傳時(shí)間： 2014-01-19
上傳用戶(hù)：chongcongying
資源簡(jiǎn)介：This application report describes the use of Timer_A3 to decode RC5 and SIRC TV IR remote control signals. The decoder described in this report is interrupt-driven and operates a background function using specific features the Timer_A3. Onl...
上傳時(shí)間： 2014-01-01
上傳用戶(hù)：qq21508895
資源簡(jiǎn)介：This paper investigates the Design of joint frequency offset and carrier phase estimation of a multi-frequency time division multiple access (MF-TDMA) demodulator that is applied to a digital video broadcasting—return channel system via...
上傳時(shí)間： 2015-12-30
上傳用戶(hù)：ls530720646
資源簡(jiǎn)介：Design PATTERNS JAVA COMPANION Design patterns began to be recognized more formally in the early 1990s by Helm (1990) and Erich Gamma (1992), who described patterns incorporated in the GUI application framework, ET++. The culmination of ...
上傳時(shí)間： 2016-02-27
上傳用戶(hù)：大三三
資源簡(jiǎn)介：THIS Design IS PROVIDED TO YOU "AS IS". XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FI...
上傳時(shí)間： 2016-03-21
上傳用戶(hù)：1427796291
資源簡(jiǎn)介：Design of Integrated Circuits for Optical Communications deals with the Design of high-speed integrated circuits for optical communication systems. Written for both students and practicing engineers, the book systematically takes the reader...
上傳時(shí)間： 2013-12-21
上傳用戶(hù)：zhouchang199
資源簡(jiǎn)介：The Window Design Method The basic idea behind the Design of linear-phase FIR filters using the window method is to choose a proper ideal frequency-selective filter [which always has a noncausal, infinite duration impulse response] and t...
上傳時(shí)間： 2017-03-20
上傳用戶(hù)：PresidentHuang
資源簡(jiǎn)介：This paper will discuss the Design of an asynchronous FIFO,Asynchronous FIFOs are widely used in the computer networking industry to receive data at a particular frequency and transmit them at another frequency. An asynchronous FIFO has t...
上傳時(shí)間： 2013-12-09
上傳用戶(hù)：Thuan
