AD公司DSP程序，用于芯片存儲器測試，可以定位到每一個bit
上傳時間： 2015-05-25
上傳用戶：ynzfm
The HD66773, controller driver LSI, displays 132RGB-by-176 dot graphics on TFT displays in 260,000 colors. The HD66773’s bit-operation functions, 18-bit high-speed bus interface, and high-speed RAMwrite functions enable efficient data transfer and high-speed rewriting of data to the graphic RAM.
標簽： displays controller graphics RGB-by
上傳時間： 2014-06-19
上傳用戶：stvnash
ITU-T Recommendation V.90 98年9月版本 A DIGITAL MODEM AND ANALOGUE MODEM PAIR FOR USE ON THE PUBLIC SWITCHED TELEPHONE NETWORK (PSTN) AT DATA SIGNALLING RATES OF UP TO 56 000 bit/s DOWNSTREAM AND UP TO 33 600 bit/s UPSTREAM
標簽： MODEM Recommendation ANALOGUE DIGITAL
上傳時間： 2014-01-17
上傳用戶：hn891122
LZW壓縮和解壓縮程序 lzw.c 主要的功能模塊 bitio.c/bitio.h 一些支撐函數，支持以比特(bit)為單位的文件I/O 用法： 壓縮 lzw E <in-file> <out-file> 解壓縮 lzw D <in-file> <out-file> 壓縮時，讀入<in-file>中內容，壓縮后存入<out-file>中，得到壓縮文件。 解壓縮時，讀入<in-file>中內容，將結果存入<out-file>中，得到原文件。 本代碼在linux+gcc/windows+vc下經過測試，為了使讀者容易理解算法本身， 算法實現中僅采用了簡單的錯誤處理機制和優化。
上傳時間： 2015-06-08
上傳用戶：chenbhdt
使用java編寫的LSB圖像信息隱藏算法演示程序，可以將任何符合大小限制的文件拆分為一個一個bit隱藏到非壓縮bmp圖像中。支持在隱藏前通過zip類對文件進行壓縮
上傳時間： 2015-06-09
上傳用戶：xuanchangri
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit Internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag
標簽： 8226 Programmable Compatible In-System
上傳時間： 2015-06-27
上傳用戶：dianxin61
8位相等比較器，比較8位數是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn
上傳時間： 2015-07-02
上傳用戶：colinal
Avalon_VGA，-- This design provides an interface to the Alcahest VGA daughter card. -- The design comprises of an 8-bit VGA driver with Avalon bus interfaces. There are a total of -- three Avalon interfaces.
標簽： Avalon_VGA
上傳時間： 2015-07-07
上傳用戶：kikye
Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model
標簽： Algorithm Decoder DVB-RCS Release
上傳時間： 2015-07-10
上傳用戶：清風冷雨
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
