1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input CLock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標簽： DDR4
上傳時間： 2022-01-09
上傳用戶：
ADS8329 Verilog fpga 驅(qū)動源碼，2.7V 至 5.5V 16 位 1MSPS 串行模數(shù)轉(zhuǎn)換器 ADC芯片ADS8329數(shù)據(jù)采集的verilog代碼，已經(jīng)用在工程中，可以做為你的設計參考。( input CLock, input timer_clk_r, input reset, output reg sample_over, output reg ad_convn, input ad_eocn, output reg ad_csn, output reg ad_clk, input ad_dout, output reg ad_din, output reg [15:0] ad_data_lock);reg [15:0] ad_data_old;reg [15:0] ad_data_new; reg [19:0] ad_data_temp; reg [15:0] ad_data;reg [4:0] ad_data_cnt;reg [4:0] ad_spi_cnt; reg [5:0] time_dly_cnt; parameter [3:0] state_mac_IDLE = 0, state_mac_0 = 1, state_mac_1 = 2, state_mac_2 = 3, state_mac_3 = 4, state_mac_4 = 5, state_mac_5 = 6, state_mac_6 = 7, state_mac_7 = 8, state_mac_8 = 9, state_mac_9 = 10, state_mac_10 = 11, state_mac_11 = 12, state_mac_12 = 13, state_mac_13 = 14, state_mac_14 = 15; reg [3:0] state_curr;reg [3:0] state_next;
標簽： ads8329 verilog fpga 驅(qū)動
上傳時間： 2022-01-30
上傳用戶：1208020161
spi 通信的master部分使用的verilog語言實現(xiàn)，可以做為你的設計參考。module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,dout,done,rdata); input rstb,clk,mlb,start; input [7:0] tdat; //transmit data input [1:0] cdiv; //CLock divider input din; output reg ss; output reg sck; output reg dout; output reg done; output reg [7:0] rdata; //received dataparameter idle=2'b00; parameter send=2'b10; parameter finish=2'b11; reg [1:0] cur,nxt; reg [7:0] treg,rreg; reg [3:0] nbit; reg [4:0] mid,cnt; reg shift,clr;
上傳時間： 2022-02-03
上傳用戶：
STM32L053C8T6數(shù)據(jù)手冊Features ? Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40 to 125 °C temperature range – 0.27 μA Standby mode (2 wakeup pins) – 0.4 μA Stop mode (16 wakeup lines) – 0.8 μA Stop mode + RTC + 8 KB RAM retention – 139 μA/MHz Run mode at 32 MHz – 3.5 μs wakeup time (from RAM) – 5 μs wakeup time (from Flash) ? Core: ARM? 32-bit Cortex?-M0+ with MPU – From 32 kHz up to 32 MHz max. – 0.95 DMIPS/MHz ? Reset and supply management – Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds – Ultralow power POR/PDR – Programmable voltage detector (PVD) ? CLock sources – 1 to 25 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – High speed internal 16 MHz factory-trimmed RC (+/- 1%) – Internal low-power 37 kHz RC – Internal multispeed low-power 65 kHz to 4.2 MHz RC – PLL for CPU CLock ? Pre-programmed bootloader – USART, SPI supported ? Development support – Serial wire debug supported ? Up to 51 fast I/Os (45 I/Os 5V tolerant) ? Memories – Up to 64 KB Flash with ECC – 8KB RAM – 2 KB of data EEPROM with ECC – 20-byte backup register
標簽： stm32l053c8t6
上傳時間： 2022-02-06
上傳用戶：
電子書-RTL Design Style Guide for Verilog HDL540頁A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the CLock signal is input to the CLock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
標簽： RTL verilog hdl
上傳時間： 2022-03-21
上傳用戶：canderile
本文首次設計并驗證了基于macom三合一芯片設計的光模塊電路,該電路旨在提供一種滿足SFF-8472中規(guī)定的數(shù)字診斷功能的低成本SFP+模塊。電路采用激光器驅(qū)動、限幅放大器、控制器以及時鐘恢復單元集成的單芯片,在保證高精度數(shù)字診斷功能基礎(chǔ)上,實現(xiàn)了低成本高可靠的特點。該電路在光接收接口組件與激光器驅(qū)動和限幅放大器單元的限幅放大器部分之間接入濾波器來提高模塊的靈敏度及信號質(zhì)量。在控制器單元的數(shù)字電位器的引腳上采用外加電阻的方式避免出現(xiàn)上電不發(fā)光的故障問題。該研究結(jié)果為下一代SFP-DD光模塊設計與開發(fā)工作,奠定了一定的理論與實踐基礎(chǔ)。This paper designs and validates the optical module circuit based on the MACOM Trinity chip for the first time.This circuit aims to provide a low-cost SFP module which meets the digital diagnosis function specified in SFF-8472.The circuit uses a single chip integrated with laser driver,limiting amplifier,controller and CLock recovery unit.On the basis of ensuring high precision digital diagnosis function,it achieves the characteristics of low cost and high reliability.The circuit connects a filter between the optical receiving interface module and the limiting amplifier part of the laser driver and limiting amplifier unit to improve the sensitivity and signal quality of the module.The pin of the digital potentiometer in the controller unit is equipped with an external resistance to avoid the problem of power failure.The research results lay a theoretical and practical foundation for optical module design in high-speed data center.
上傳時間： 2022-04-03
上傳用戶：
The GL823K integrates a high speed 8051 microprocessor and a high efficiency hardware engine for the best data transfer performance between USB and flash card interfaces. Its pin assignment design fits to card sockets to provide easier PCB layout. Inside the chip, it integrates 5V to 3.3V regulator, 3.3V to 1.8V regulator and power MOSFETs and it enables the function of on-chip CLock source (OCCS) which means no external 12MHz XTAL is needed and that effectively reduces the total BOM cost.
上傳時間： 2022-04-27
上傳用戶：qdxqdxqdxqdx
STM32F103開發(fā)板 DHT11溫濕度DS18B20 氣體MQ-2光敏聲控雨滴傳感器實驗程序**--------------------------------------------------------------------------------------------------------** Created by: FiYu** Created date: 2015-12-12** Version: 1.0** Descriptions: DHT11溫濕度傳感器實驗 **--------------------------------------------------------------------------------------------------------** Modified by: FiYu** Modified date: ** Version: ** Descriptions: ** Rechecked by: **********************************************************************************************************/#include "stm32f10x.h"#include "delay.h"#include "dht11.h"#include "usart.h"DHT11_Data_TypeDef DHT11_Data;/************************************************************************************** * 描 述 : GPIO/USART1初始化配置 * 入 參 : 無 * 返回值 : 無 **************************************************************************************/void GPIO_Configuration(void){ GPIO_InitTypeDef GPIO_InitStructure; /* Enable the GPIO_LED CLock */ RCC_APB2PeriphCLockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO , ENABLE); GPIO_DeInit(GPIOB); //將外設GPIOA寄存器重設為缺省值 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //推挽輸出 GPIO_Init(GPIOB, &GPIO_InitStructure); GPIO_DeInit(GPIOA); //將外設GPIOA寄存器重設為缺省值 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; //推挽輸出 GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; //浮空輸入 GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_SetBits(GPIOB , GPIO_Pin_9); //初始狀態(tài)，熄滅指示燈LED1}/************************************************************************************** * 描 述 : 串口顯示實時溫濕度 * 入 參 : 無 * 返回值 : 無 **************************************************************************************/void DHT11_SCAN(void){ if( Read_DHT11(&DHT11_Data)==SUCCESS) { printf("\r\n讀取DHT11成功!\r\n\r\n濕度為%d.%d ％RH ，溫度為 %d.%d℃ \r\n",\ DHT11_Data.humi_int,DHT11_Data.humi_deci,DHT11_Data.temp_int,DHT11_Data.temp_deci); //printf("\r\n 濕度:%d,溫度:%d \r\n" ,DHT11_Data.humi_int,DHT11_Data.temp_int); } else { printf("Read DHT11 ERROR!\r\n"); }}/************************************************************************************** * 描 述 : MAIN函數(shù) * 入 參 : 無 * 返回值 : 無 **************************************************************************************/int main(void){ SystemInit(); //設置系統(tǒng)時鐘72MHZ GPIO_Configuration(); USART1_Init(); //初始化配置TIM DHT11_GPIO_Config(); // 初始化溫濕度傳感器PB1引腳初始時為推挽輸出 GPIO_ResetBits(GPIOB , GPIO_Pin_9); delay_ms(500); while(1) { GPIO_SetBits(GPIOB , GPIO_Pin_9); DHT11_SCAN(); //實時顯示溫濕度 delay_ms(1500); } }
上傳時間： 2022-05-03
上傳用戶：得之我幸78
說明： 基于stm32f103c8t6單片機的RTC實時時鐘源碼，固件庫為3.5版本(Based on the real-time CLock source stm32f103c8t6 MCU RTC firmware library version 3.5)
上傳時間： 2022-05-16
上傳用戶：得之我幸78
說明： 51單片機電子時鐘，含proteus仿真和keil工程源碼(51 single-chip electronic CLock, including the proteus simulation and keil project source)
上傳時間： 2022-05-27
上傳用戶：
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