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In-<b>CIRCUIT</b>

  • CoolMOS導通電阻分析及與VDMOS的比較

    為了克服傳統功率MOS 導通電阻與擊穿電壓之間的矛盾,提出了一種新的理想器件結構,稱為超級結器件或Cool2MOS ,CoolMOS 由一系列的P 型和N 型半導體薄層交替排列組成。在截止態時,由于p 型和n 型層中的耗盡區電場產生相互補償效應,使p 型和n 型層的摻雜濃度可以做的很高而不會引起器件擊穿電壓的下降。導通時,這種高濃度的摻雜使器件的導通電阻明顯降低。由于CoolMOS 的這種獨特器件結構,使它的電性能優于傳統功率MOS。本文對CoolMOS 導通電阻與擊穿電壓關系的理論計算表明,對CoolMOS 橫向器件: Ron ·A = C ·V 2B ,對縱向器件: Ron ·A = C ·V B ,與縱向DMOS 導通電阻與擊穿電壓之間Ron ·A = C ·V 2. 5B 的關系相比,CoolMOS 的導通電阻降低了約兩個數量級。

    標簽: CoolMOS VDMOS 導通電阻

    上傳時間: 2013-10-21

    上傳用戶:1427796291

  • 雙絞線和低通濾波器降低EMI_RFI

    Abstract: Alexander Graham Bell patented twisted pair wires in 1881. We still use them today because they work so well. In addition we have the advantage ofincredible computer power within our world. Circuit simulators and filter design programs are available for little or no cost. We combine the twisted pair and lowpassfilters to produce spectacular rejection of radio frequency interference (RFI) and electromagnetic interference (EMI). We also illustrate use of a precision resistorarray to produce a customizable differential amplifier. The precision resistors set the gain and common mode rejection ratios, while we choose the frequencyresponse.

    標簽: EMI_RFI 雙絞線 低通濾波器

    上傳時間: 2014-11-26

    上傳用戶:Vici

  • 利用數字電位器調整并校準升壓型DC-DC轉換器

    The purpose of this application note is to show an example of how a digital potentiometer can be used in thefeedback loop of a step-up DC-DC converter to provide calibration and/or adjustment of the output voltage.The example circuit uses a MAX5025 step-up DC-DC converter (capable of generating up to 36V,120mWmax) in conjunction with a DS1845, 256 position, NV digital potentiometer. For this example, the desiredoutput voltage is 32V, which is generated from an input supply of 5V. The output voltage can be adjusted in35mV increments (near 32V) and span a range wide enough to account for resistance, potentiometer and DCDCconverter tolerances (27.6V to 36.7V).

    標簽: DC-DC 數字電位器 升壓型 校準

    上傳時間: 2014-12-23

    上傳用戶:781354052

  • XAPP854-數字鎖相環(DPLL)參考設計

    Many applications require a clock signal to be synchronous, phase-locked, or derived fromanother signal, such as a data signal or another clock. This type of clock circuit is important in

    標簽: XAPP DPLL 854 數字鎖相環

    上傳時間: 2014-12-23

    上傳用戶:qq21508895

  • Stabilize Your Transimpedance Amplifier

      Abstract: Transimpedance amplifiers (TIAs) are widely used to translate the current output of sensors like photodiode-to-voltagesignals, since several circuits and instruments can only accept voltage input. An operational amplifier with a feedback resistor fromoutput to the inverting input is the most straightforward implementation of such a TIA. However, even this simple TIA circuit requirescareful trade-offs among noise gain, offset voltage, bandwidth, and stability. Clearly stability in a TIA is essential for good, reliableperformance. This application note explains the empirical calculations for assessing stability and then shows how to fine-tune theselection of the feedback phase-compensation capacitor.

    標簽: Transimpedance Stabilize Amplifier Your

    上傳時間: 2013-11-13

    上傳用戶:daoyue

  • 數字集成電路設計Digital Integrated Circuit Design

      This unique guide to designing digital VLSI circuits takes a top-down approach, reflecting the natureof the design process in industry. Starting with architecture design, the book explains the why andhow of digital design, using the physics that designers need to know, and no more.Covering system and component aspects, design verification, VHDL modelling, clocking, signalintegrity, layout, electricaloverstress, field-programmable logic, economic issues, and more, thescope of the book is singularly comprehensive.

    標簽: Integrated Digital Circuit Design

    上傳時間: 2013-11-04

    上傳用戶:life840315

  • 你的PLD是亞穩態嗎

      This application note provides a detailed description of themetastable behavior in PLDs from both circuit and statisticalviewpoints. Additionally, the information on the metastablecharacteristics of Cypress PLDs presented here can help youachieve any desired degree of reliability.

    標簽: PLD 亞穩態

    上傳時間: 2013-10-23

    上傳用戶:gtzj

  • 定點乘法器設計(中文)

       定點乘法器設計(中文)  運算符:   + 對其兩邊的數據作加法操作; A + B   - 從左邊的數據中減去右邊的數據; A - B   - 對跟在其后的數據作取補操作,即用0減去跟在其后的數據; - B   * 對其兩邊的數據作乘法操作; A * B   & 對其兩邊的數據按位作與操作; A & B   # 對其兩邊的數據按位作或操作; A # B   @ 對其兩邊的數據按位作異或操作; A @ B   ~ 對跟在其后的數據作按位取反操作; ~ B   << 以右邊的數據為移位量將左邊的數據左移; A << B   $ 將其兩邊的數據按從左至右順序拼接; A $ B

    標簽: 定點 乘法器設計

    上傳時間: 2013-12-17

    上傳用戶:trepb001

  • IC封裝熱計算研究

    Many thermal metrics exist for integrated circuit (IC) packages ranging from θja to Ψjt.Often, these thermal metrics are misapplied by customers who try to use them to estimate junction temperatures in their systems.

    標簽: IC封裝 計算

    上傳時間: 2013-10-18

    上傳用戶:貓愛薛定諤

  • RF至數字接收器的信號鏈噪聲分析

      Designers of signal receiver systems often need to performcascaded chain analysis of system performancefrom the antenna all the way to the ADC. Noise is a criticalparameter in the chain analysis because it limits theoverall sensitivity of the receiver. An application’s noiserequirement has a signifi cant infl uence on the systemtopology, since the choice of topology strives to optimizethe overall signal-to-noise ratio, dynamic range andseveral other parameters. One problem in noise calculationsis translating between the various units used by thecomponents in the chain: namely the RF, IF/baseband,and digital (ADC) sections of the circuit.

    標簽: 數字接收器 信號鏈 噪聲分析

    上傳時間: 2014-12-05

    上傳用戶:cylnpy

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