SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
標(biāo)簽： FPGA PLD 數(shù)據(jù)加密
上傳時(shí)間： 2013-10-20
上傳用戶：磊子226
FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development
標(biāo)簽： Methodology Design Reuse FPGA
上傳時(shí)間： 2013-11-01
上傳用戶：shawvi
Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
上傳時(shí)間： 2013-10-22
上傳用戶：lmq0059
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
標(biāo)簽： 賽靈思 電機(jī)控制 開發(fā)套件 英文
上傳時(shí)間： 2013-10-28
上傳用戶：wujijunshi
Attributes, Constraints, and Carry Logic Overview Information for Mentor Customers Schematic Syntax UCF/NCF File Syntax Attributes/Logical Constraints Placement Constraints Relative Location (RLOC) Constraints Timing Constraints Physical Constraints Relationally Placed Macros (RPM) Carry Logic in XC4000 FPGAs Carry Logic in XC5200 FPGAs
標(biāo)簽： Constraints Information Attributes Customers
上傳時(shí)間： 2015-05-12
上傳用戶：cc1015285075
The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification.
標(biāo)簽： introduction workshop provides advanced
上傳時(shí)間： 2014-12-06
上傳用戶：sammi
關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates implementing pipelines circuits
上傳時(shí)間： 2015-07-26
上傳用戶：CHINA526
AccelDSP Synthesis Tool Floating-Point to Fixed-Point Conversion of MATLAB Algorithms Targeting FPGAs
標(biāo)簽： Floating-Point Fixed-Point Conversion Algorithms
上傳時(shí)間： 2014-01-14
上傳用戶：wangzhen1990
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計(jì)文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時(shí)間： 2014-11-01
上傳用戶：l254587896
1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis 2. fpga implemention of a median filter 3. fpga implementation of digital filters 4.hardware acceleration of edge detection algorithm on FPGAs 5.implementation and evaluation of image processing algorithms on reconfigurable architecture using C-based hardware descriptive languages 6. implementing 2D median filter in FPGAs 7.視頻圖像處理與分析的網(wǎng)絡(luò)資源
標(biāo)簽： implementation reconstruction hyperspectral algorithm
上傳時(shí)間： 2014-01-10
上傳用戶：894898248
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