應(yīng)用于電動(dòng)汽車驅(qū)動(dòng)領(lǐng)域的永磁同步電機(jī)交流驅(qū)動(dòng)系統(tǒng)是由永磁同步電機(jī)、電力電子技術(shù)和控制技術(shù)相結(jié)合而形成的新型交流驅(qū)動(dòng)系統(tǒng)。因其具有良好的運(yùn)行性能而成為當(dāng)代電氣傳動(dòng)領(lǐng)域研究的熱點(diǎn)之一。 永磁同步電機(jī)是一個(gè)多變量、非線性、高強(qiáng)耦合的系統(tǒng)，其輸出轉(zhuǎn)矩與定子電流不成正比，而是復(fù)雜的函數(shù)關(guān)系，因此要得到好的控制性能，需要進(jìn)行磁場解耦。矢量變換控制技術(shù)正好適用于永磁同步電機(jī)的這種特點(diǎn)。 本文在數(shù)字電機(jī)控制專用DSP芯片TMS320LF2407的基礎(chǔ)上，以永磁同步電機(jī)為研究對(duì)象，對(duì)其矢量控制技術(shù)進(jìn)行了研究和設(shè)計(jì)。 首先課題根據(jù)永磁同步電機(jī)實(shí)際物理模型，分析推導(dǎo)得到了永磁同步電機(jī)的三相靜止坐標(biāo)系下及兩相旋轉(zhuǎn)坐標(biāo)系下的數(shù)學(xué)模型。 接著課題對(duì)永磁同步電機(jī)運(yùn)行特性進(jìn)行了分析和研究。在此基礎(chǔ)上，課題提出了一種新型的永磁同步電機(jī)矢量控制系統(tǒng)，在這個(gè)系統(tǒng)上，課題提出了應(yīng)用不同矢量控制策略的矢量控制方法，并對(duì)其做了仿真驗(yàn)證。 結(jié)果表明，課題設(shè)計(jì)的系統(tǒng)以及應(yīng)用不同矢量控制策略的矢量控制方法準(zhǔn)確可行。 這個(gè)控制系統(tǒng)便于實(shí)現(xiàn)多種矢量控制方法，為永磁同步電機(jī)擴(kuò)速增效提供了理論平臺(tái)。 在理論分析、仿真通過基礎(chǔ)上，課題對(duì)驅(qū)動(dòng)系統(tǒng)的硬件和軟件兩個(gè)方面進(jìn)行了具體的設(shè)計(jì)。 課題完成了DSP控制系統(tǒng)關(guān)鍵硬件電路的設(shè)計(jì)，并設(shè)計(jì)制作了一塊應(yīng)用SCALE模塊的IGBT驅(qū)動(dòng)電路，此驅(qū)動(dòng)電路響應(yīng)迅速、抗干擾性強(qiáng)，驅(qū)動(dòng)性能優(yōu)越。此外，課題完成了永磁同步電機(jī)矢量控制系統(tǒng)全數(shù)字化設(shè)計(jì)，調(diào)試通過了速度位置檢測、電流檢測、PI調(diào)節(jié)、坐標(biāo)變換等應(yīng)用模塊。 課題最后對(duì)整個(gè)系統(tǒng)的做了全面的總結(jié)，并對(duì)今后的工作方向進(jìn)行了展望。
標(biāo)簽： DSP 永磁同步電機(jī) 技術(shù)研究
上傳時(shí)間： 2013-06-22
上傳用戶：firstbyte
為了克服傳統(tǒng)的局部特征匹配算法對(duì)噪聲和圖像灰度非線性變換敏感的不足，提出了基于SIFT（SCALE Invariant Feature Transform）描述算子的特征匹配算法。該算法首先
上傳時(shí)間： 2013-04-24
上傳用戶：hphh
Abstract: Using a DAC and a microprocessor supervisor, the system safety can be improved in industrial controllers, programmablelogiccontrollers (PLC), and data-acquisition systems. The analog output is set to zero-SCALE (or pin-programmable midSCALE) when amicroprocessor failure, optocoupler failure, or undervoltage condition occurs. A simple application is shown on how to implement thisfunction.
上傳時(shí)間： 2013-10-17
上傳用戶：sjb555
Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full SCALE. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full SCALE Error): The difference between theoutput voltage (or current) with full SCALE input code and theideal voltage (or current) that should exist with a full SCALE inputcode.Gain Temperature Coefficient (Full SCALE TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full SCALE).Can be expressed as a percentage of full SCALE or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full SCALE voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.
標(biāo)簽： Converters Defini DAC
上傳時(shí)間： 2013-10-30
上傳用戶：stvnash
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full SCALE input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero SCALE Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
標(biāo)簽： Converter Defi ADC 轉(zhuǎn)換器
上傳時(shí)間： 2013-11-12
上傳用戶：pans0ul
數(shù)字與模擬電路設(shè)計(jì)技巧IC與LSI的功能大幅提升使得高壓電路與電力電路除外，幾乎所有的電路都是由半導(dǎo)體組件所構(gòu)成，雖然半導(dǎo)體組件高速、高頻化時(shí)會(huì)有EMI的困擾，不過為了充分發(fā)揮半導(dǎo)體組件應(yīng)有的性能，電路板設(shè)計(jì)與封裝技術(shù)仍具有決定性的影響。 模擬與數(shù)字技術(shù)的融合由于IC與LSI半導(dǎo)體本身的高速化，同時(shí)為了使機(jī)器達(dá)到正常動(dòng)作的目的，因此技術(shù)上的跨越競爭越來越激烈。雖然構(gòu)成系統(tǒng)的電路未必有clock設(shè)計(jì)，但是毫無疑問的是系統(tǒng)的可靠度是建立在電子組件的選用、封裝技術(shù)、電路設(shè)計(jì)與成本，以及如何防止噪訊的產(chǎn)生與噪訊外漏等綜合考慮。機(jī)器小型化、高速化、多功能化使得低頻/高頻、大功率信號(hào)/小功率信號(hào)、高輸出阻抗/低輸出阻抗、大電流/小電流、模擬/數(shù)字電路，經(jīng)常出現(xiàn)在同一個(gè)高封裝密度電路板，設(shè)計(jì)者身處如此的環(huán)境必需面對(duì)前所未有的設(shè)計(jì)思維挑戰(zhàn)，例如高穩(wěn)定性電路與吵雜(noisy)性電路為鄰時(shí)，如果未將噪訊入侵高穩(wěn)定性電路的對(duì)策視為設(shè)計(jì)重點(diǎn)，事后反復(fù)的設(shè)計(jì)變更往往成為無解的夢魘。模擬電路與高速數(shù)字電路混合設(shè)計(jì)也是如此，假設(shè)微小模擬信號(hào)增幅后再將full SCALE 5V的模擬信號(hào)，利用10bit A/D轉(zhuǎn)換器轉(zhuǎn)換成數(shù)字信號(hào)，由于分割幅寬祇有4.9mV，因此要正確讀取該電壓level并非易事，結(jié)果造成10bit以上的A/D轉(zhuǎn)換器面臨無法順利運(yùn)作的窘境。另一典型實(shí)例是使用示波器量測某數(shù)字電路基板兩點(diǎn)相隔10cm的ground電位，理論上ground電位應(yīng)該是零，然而實(shí)際上卻可觀測到4.9mV數(shù)倍甚至數(shù)十倍的脈沖噪訊(pulse noise)，如果該電位差是由模擬與數(shù)字混合電路的grand所造成的話，要測得4.9 mV的信號(hào)根本是不可能的事情，也就是說為了使模擬與數(shù)字混合電路順利動(dòng)作，必需在封裝與電路設(shè)計(jì)有相對(duì)的對(duì)策，尤其是數(shù)字電路switching時(shí)，ground vance noise不會(huì)入侵analogue ground的防護(hù)對(duì)策，同時(shí)還需充分檢討各電路產(chǎn)生的電流回路(route)與電流大小，依此結(jié)果排除各種可能的干擾因素。以上介紹的實(shí)例都是設(shè)計(jì)模擬與數(shù)字混合電路時(shí)經(jīng)常遇到的瓶頸，如果是設(shè)計(jì)12bit以上A/D轉(zhuǎn)換器時(shí)，它的困難度會(huì)更加復(fù)雜。
標(biāo)簽： 數(shù)字 模擬電路 設(shè)計(jì)技巧
上傳時(shí)間： 2013-11-16
上傳用戶：731140412
為深入了解基于UC3854A控制的PFC變換器中的動(dòng)力學(xué)特性，研究系統(tǒng)參數(shù)變化對(duì)變換器中分岔現(xiàn)象的影響，在建立Boost PFC變換器雙閉環(huán)數(shù)學(xué)模型的基礎(chǔ)上，用Matlab軟件對(duì)變換器中慢時(shí)標(biāo)分岔及混沌等不穩(wěn)定現(xiàn)象進(jìn)行了仿真。在對(duì)PFC變換器中慢時(shí)標(biāo)分岔現(xiàn)象仿真的基礎(chǔ)上，分析了系統(tǒng)參數(shù)變化對(duì)分岔點(diǎn)的影響，并進(jìn)行了仿真驗(yàn)證。仿真結(jié)果清晰地顯示了輸入整流電壓的幅值變化對(duì)系統(tǒng)分岔點(diǎn)的影響。 Abstract: In order to better understand the dynamics characteristic of power factor correction converter based on UC3854A， and make the way that parameters change influences the bifurcation phenomena of the system clearly. The math model of the two closed loop circuits to the Boost PFC （Power Factor Correction） converter controller was built. Then， with the help of Matlab， the simulation for nonlinear phenomena such as chaos and slow-SCALE bifurcation in the PFC converter was made. Finally the factors that have influence to the phenomenon of bifurcation under slow-SCALE in PFC converter were analyzed. The simulation results clearly show the parameters change influences the bifurcation point of the system.
上傳時(shí)間： 2013-10-17
上傳用戶：杜瑩12345
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-SCALE functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時(shí)間： 2013-10-22
上傳用戶：ztj182002
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-SCALE functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時(shí)間： 2013-11-21
上傳用戶：不懂夜的黑
數(shù)字與模擬電路設(shè)計(jì)技巧IC與LSI的功能大幅提升使得高壓電路與電力電路除外，幾乎所有的電路都是由半導(dǎo)體組件所構(gòu)成，雖然半導(dǎo)體組件高速、高頻化時(shí)會(huì)有EMI的困擾，不過為了充分發(fā)揮半導(dǎo)體組件應(yīng)有的性能，電路板設(shè)計(jì)與封裝技術(shù)仍具有決定性的影響。 模擬與數(shù)字技術(shù)的融合由于IC與LSI半導(dǎo)體本身的高速化，同時(shí)為了使機(jī)器達(dá)到正常動(dòng)作的目的，因此技術(shù)上的跨越競爭越來越激烈。雖然構(gòu)成系統(tǒng)的電路未必有clock設(shè)計(jì)，但是毫無疑問的是系統(tǒng)的可靠度是建立在電子組件的選用、封裝技術(shù)、電路設(shè)計(jì)與成本，以及如何防止噪訊的產(chǎn)生與噪訊外漏等綜合考慮。機(jī)器小型化、高速化、多功能化使得低頻/高頻、大功率信號(hào)/小功率信號(hào)、高輸出阻抗/低輸出阻抗、大電流/小電流、模擬/數(shù)字電路，經(jīng)常出現(xiàn)在同一個(gè)高封裝密度電路板，設(shè)計(jì)者身處如此的環(huán)境必需面對(duì)前所未有的設(shè)計(jì)思維挑戰(zhàn)，例如高穩(wěn)定性電路與吵雜(noisy)性電路為鄰時(shí)，如果未將噪訊入侵高穩(wěn)定性電路的對(duì)策視為設(shè)計(jì)重點(diǎn)，事后反復(fù)的設(shè)計(jì)變更往往成為無解的夢魘。模擬電路與高速數(shù)字電路混合設(shè)計(jì)也是如此，假設(shè)微小模擬信號(hào)增幅后再將full SCALE 5V的模擬信號(hào)，利用10bit A/D轉(zhuǎn)換器轉(zhuǎn)換成數(shù)字信號(hào)，由于分割幅寬祇有4.9mV，因此要正確讀取該電壓level并非易事，結(jié)果造成10bit以上的A/D轉(zhuǎn)換器面臨無法順利運(yùn)作的窘境。另一典型實(shí)例是使用示波器量測某數(shù)字電路基板兩點(diǎn)相隔10cm的ground電位，理論上ground電位應(yīng)該是零，然而實(shí)際上卻可觀測到4.9mV數(shù)倍甚至數(shù)十倍的脈沖噪訊(pulse noise)，如果該電位差是由模擬與數(shù)字混合電路的grand所造成的話，要測得4.9 mV的信號(hào)根本是不可能的事情，也就是說為了使模擬與數(shù)字混合電路順利動(dòng)作，必需在封裝與電路設(shè)計(jì)有相對(duì)的對(duì)策，尤其是數(shù)字電路switching時(shí)，ground vance noise不會(huì)入侵analogue ground的防護(hù)對(duì)策，同時(shí)還需充分檢討各電路產(chǎn)生的電流回路(route)與電流大小，依此結(jié)果排除各種可能的干擾因素。以上介紹的實(shí)例都是設(shè)計(jì)模擬與數(shù)字混合電路時(shí)經(jīng)常遇到的瓶頸，如果是設(shè)計(jì)12bit以上A/D轉(zhuǎn)換器時(shí)，它的困難度會(huì)更加復(fù)雜。
標(biāo)簽： 數(shù)字 模擬電路 設(shè)計(jì)技巧
上傳時(shí)間： 2014-02-12
上傳用戶：wenyuoo
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